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FH8065401488914
Volume 2—Power Management Controller (PMC)—C2000 Product Family
Architectural Overview
Intel
®
Atom™ Processor C2000 Product Family for Microserver
Datasheet, Vol. 2 of 3
September 2014
448
Order Number: 330061-002US
19.3.1
Reset Behavior
19.3.1.1
Overview
There are numerous sources that can cause the SoC to reset the platform. There are
also numerous types of resets that can result.
and the reset type list that
follows describe these sources and the SoC reaction. See
for the SoC hardware-signal interface for power, resets, and
state transitions.
Table 19-4. SoC Reset Sources
Trigger
Description
Type of Reset (See List below)
Write of 0Eh to CF9h Register
A write of 0Eh to the CF9h register
2
Write of 06h to CF9h Register
A write of 06h to the CF9h register
1
PMU_RESETBUTTON_B and CF9h
Bit 3 = 0
The user presses the reset button causing the
CPU_RESET_B pin to go active (after the
debounce logic).
1
PMU_RESETBUTTON_B and CF9h
Bit 3 = 1
The user presses the reset button causing the
CPU_RESET_B pin to go active (after the
debounce logic).
2
TCO Watchdog Timer
The TCO timer reaches zero two times.
1
Power Failure
The COREPWROK signal goes inactive in S0.
4
S5
The SoC is reset when going into the S5 state.
3
SoC
Internal Thermal Trip
The internal thermal sensor signals a
catastrophic temperature condition— transition
to S5 and reset asserts.
5
PMU_PWRBTN_B (Power Button
Override)
A 4-second press causes a transition to S5 (and
reset asserts).
5
CPU Shutdown with Policy to Assert
PMU_PLTRST_B
A shutdown special cycle from the CPU can
cause either INIT or CF9h-style PLTRST.
4; if the CF9h Global Reset Bit = 1b, else
2; if the CF9h Register Bit 3 = 1b, else 1
Write of 06h or 0Eh to CF9h
Register
CF9h Global Reset Bit = 1b
4
Host Partition Reset Entry Timeout
The host partition reset entry sequence took
longer than the allowed time out value
(presumably due to a failure to receive one of
the internal or external handshakes).
4
S5 Entry Timeout
An S5 entry sequence took longer than the
allowed time out value (presumably due to a
failure to receive one of the internal or external
handshakes).
5
PMC Watchdog Timer
A firmware hang watchdog time out is detected
in the PMC platform.
5