Intel E3815 FH8065301567411 Scheda Tecnica
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FH8065301567411
Power Up and Reset Sequence
Intel
®
Atom™ Processor E3800 Product Family
106
Datasheet
Table 61. Types of Resets (Sheet 1 of 2)
Trigger
Description
Note
Write of 0Eh to Reset Control
Register (RST_CNT)
Register (RST_CNT)
Write of 0Eh to the Reset Control
register
register
Host Reset with Power Cycle
Write of 06h to Reset Control
Register (RST_CNT)
Register (RST_CNT)
Write of 06h to the Reset Control
register
register
Host Reset without Power Cycle
with PMC_PLTRST# assertion
with PMC_PLTRST# assertion
PMC_RSTBTN# &
RST_CNT.full_rst = 0
RST_CNT.full_rst = 0
User presses the reset button,
causing the PMC_RSTBTN# signal
to go active (after the debounce
logic)
causing the PMC_RSTBTN# signal
to go active (after the debounce
logic)
Host Reset without Power Cycle
PMC_PLTRST# assertion enabled/
disabled by RST_CNT.sys_rst
PMC_PLTRST# assertion enabled/
disabled by RST_CNT.sys_rst
Write of 4h to Reset Control
Register (RST_CNT)
Register (RST_CNT)
Write of 4h to Reset Control
Register (RST_CNT)
Register (RST_CNT)
Host Reset without Power Cycle
without PMC_PLTRST# assertion
without PMC_PLTRST# assertion
PMC_RSTBTN# &
RST_CNT.full_rst = 1
RST_CNT.full_rst = 1
User presses the reset button,
causing the PMC_RSTBTN# signal
to go active (after the debounce
logic)
causing the PMC_RSTBTN# signal
to go active (after the debounce
logic)
Host Reset with Power Cycle
Power Failure
PMC_CORE_PWROK signal goes
inactive in S0/S1
inactive in S0/S1
Global Reset with Power Cycle
S3/S4/S5
The processor is reset when going
to S3, S4 or S5 state
to S3, S4 or S5 state
Sx Entry
Processor Thermal Trip
The internal thermal sensor signals
a catastrophic temperature
condition – transition to S5 and
reset asserts
a catastrophic temperature
condition – transition to S5 and
reset asserts
Global Reset, Go-to-S5
PMC_PWRBTN# Power Button
Override
Override
4-second press causes transition to
S5 (and reset asserts)
S5 (and reset asserts)
Global Reset, Go-to-S5
CPU Shutdown with Policy to assert
PMC_PLTRST#
PMC_PLTRST#
Shutdown special cycle from CPU
can cause either INIT or Reset
Control-style PMC_PLTRST#
can cause either INIT or Reset
Control-style PMC_PLTRST#
Global Reset with Power Cycle (if
ETR.CF9GR = 1b)
Host Reset with Power Cycle (if
RST_CNT.full_rst= 1b),
Host Reset without Power Cycle
(others setting)
ETR.CF9GR = 1b)
Host Reset with Power Cycle (if
RST_CNT.full_rst= 1b),
Host Reset without Power Cycle
(others setting)
Write of 06h or 0Eh to Reset Control
Register (RST_CNT)
Register (RST_CNT)
ETR.CF9GR = 1b
Global Reset with Power Cycle
Host Partition Reset Entry Timeout
Host partition reset entry sequence
took longer than the allowed
timeout value (presumably due to a
failure to receive one of the internal
or external handshakes)
took longer than the allowed
timeout value (presumably due to a
failure to receive one of the internal
or external handshakes)
Global Reset with Power Cycle
S3/S4/S5 Entry Timeout
S3, S4, or S5 entry sequence took
longer than the allowed timeout
value (presumably due to a failure
to receive one of the internal or
external handshakes)
longer than the allowed timeout
value (presumably due to a failure
to receive one of the internal or
external handshakes)
Global Reset, Go-to-S5