Intel E3815 FH8065301567411 Scheda Tecnica
Codici prodotto
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
2728
Datasheet
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
D
M
A
_
PO
SIT
IO
N
_LOW
ER
_B
AS
E
_
AD
D
R
ESS
DM
A_P
O
S
IT
ION
_L
O
W
E
R
_B
AS
E_U
N
IMPL
E
M
EN
TE
D
_
B
ITS
DMA_P
O
S
ITION_BU
FFER_E
N
ABLE
Bit
Range
Default &
Access
Description
31:7
0h
RW
DMA_POSITION_LOWER_BASE_ADDRESS:
Lower 32 bits of the DMA Position Buffer
Base Address. This register field must not be written when any DMA engine is running or
the DMA transfer may be corrupted. This same address is used by the Flush Control and
must be programmed with a valid value before the FLCNRTL bit is set.
6:1
00h
RO
DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS:
Hardwired to 0 to force
128 byte buffer alignment for cache line write optimizations.
0
0h
RW
DMA_POSITION_BUFFER_ENABLE:
When this bit is set to a 1 the controller will
write the DMA positions of each of the DMA engines to the buffer in main memory
periodically typically once frame . Software can use this value to know what data in
memory is valid data. The controller must guarantee that the values in the DMA Position
Buffer that the software can read represent positions in the stream for which valid data
exists in the Stream s DMA buffer. This has particular relevance in systems which
support isochronous transfer the stream positions in the software visible memory buffer
must represent stream data which has reached the Global Observation point.