Intel E3815 FH8065301567411 Scheda Tecnica
Codici prodotto
FH8065301567411
SIO – High Speed UART
Intel
®
Atom™ Processor E3800 Product Family
4174
Datasheet
27.2.2
Clock and Reset
The BAUD rate generates from serial clock (Sclock) frequency which is based on a
fixed base/system clock (Fbase) of 100 MHz processed through an M/N divider. M/N
divider settings are found in the HSUART’s PRV_CLOCK_PARAMS register. Sclock
frequency = (Fbase*M)/N. Some useful Sclock frequencies and related M/N values are
shown below:
fixed base/system clock (Fbase) of 100 MHz processed through an M/N divider. M/N
divider settings are found in the HSUART’s PRV_CLOCK_PARAMS register. Sclock
frequency = (Fbase*M)/N. Some useful Sclock frequencies and related M/N values are
shown below:
27.2.3
Baud Rate Generator
The baud rates for the UARTs are generated with from the serial clock frequency
(Sclock) by programming the DLH and DLL registers as a divisor. The hexadecimal
value of the divisor is (IER_DLH[7:0]<<8) | RBR_THR_DLL[7:0].
(Sclock) by programming the DLH and DLL registers as a divisor. The hexadecimal
value of the divisor is (IER_DLH[7:0]<<8) | RBR_THR_DLL[7:0].
Fbase is the system clock frequency in Hz (100,000,000 in decimal when the system
clock frequency is 100 MHz.).
clock frequency is 100 MHz.).
The output baud rate is as follows:
— baud rate = (Sclock) / (16 * divisor)
Table 275. Sclock Frequencies from M/N Settings
M Value
N Value
Sclock
228 (0x120)
15625 (0x3D09)
1.84320 MHz
1024 (0x400)
3125 (0xC35)
32.7680 MHz
9216 (0x2400)
15625 (0x3D09)
58.9824 MHz
Table 276. Baud Rates Achievable with Different DLAB Settings
DLH,DLL Divisor
DLH,DLL Divisor
Hexadecimal
Baud Rate
Sclock
= 1.84320 MHz
1
0001
115200
2
0002
57600
3
0003
38400
6
0006
19200
12
000C
9600
24
0018
4800
48
0030
2400
192
00C0
600
384
0180 300
Sclock
= 58.9824 MHz
4
0004
921600
8
0008
460800
16
0010
230400
24
0018
153600
Sclock
= 32.768 MHz
8
0008
256000
16
0010
128000