Intel E3815 FH8065301567411 Scheda Tecnica
Codici prodotto
FH8065301567411
PCU – Power Management Controller (PMC)
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
4309
NOTES:
1.
Most of the status bits (except otherwise is noted) are set according to event occurrence regardless to the enable bit.
2.
GPIO status bits are set only if enable criteria is true. GPIO_ROUT[n]=10b & GPE0a_EN.x_GPIO_EN[n] for
GPE0a_STS.x_GPIO_STS[n] (SCI). GPIO_ROUT[n]=01b & ALT_GPIO_SMI. x_GPIO_SMI_EN[n]=1b for
ALT_GPIO_SMI.x_GPIO_SMI_STS[n] (SMI).
3.
When power button override occurs, the system will transition immediately to S5. The SCI will only occur after the next
wake to S0 if the residual status bit (PM1_STS_EN.PWRBTNOR_STS) is not cleared prior to setting PM1_CNT.SCI_EN.
4.
PM1_STS_EN.GBL_STS being set will cause an SCI, even if the PM1_CNT.SCI_EN bit is not set. Software must take great
care not to set the SMI_ENBIOS_RLS bit (which causes PM1_STS_EN.GBL_STS to be set) if the SCI handler is not in place.
5.
No enable bits for these SCI/SMI messages in the PMC. Enable capability should be implemented in the source unit.
6.
Sync SMI has the same message opcode toward T-Unit. Special treatment regarding this Sync SMI is holding completion
to host till SYNC_SMI_ACK message is received from T-Unit.
7.
Sync SMI has the same message opcode toward T-Unit. Special treatment regarding this Sync SMI is holding the
SSMI_ACK message to iLB till SYNC_SMI_ACK message is received from T-Unit.
8.
The G-Unit is an internal functional sub-block which forms part of the graphics functional block.
9.
The GPE0a_STS.CORE_GPIO_STS[31:24] & GPE0a_EN.CORE_GPIO_EN[31:24] register bits correspond to
GPIO_S0_SC[7:0]. GPE0a_STS.SUS_GPIO_STS[23:16] & GPE0a_EN.SUS_GPIO_EN[23:16] correspond to GPIO_S5[7:0].
10.
The ALT_GPIO_SMI.CORE_GPIO_SMI_STS[31:24] & ALT_GPIO_SMI.CORE_GPIO_SMI_EN[15:8] register bits correspond
to GPIO_S0_SC[7:0]. ALT_GPIO_SMI.SUS_GPIO_SMI_STS[23:16] & ALT_GPIO_SMI.SUS_GPIO_SMI_EN[7:0] correspond
to GPIO_S5[7:0].
ASSERT_IS_SMI
message from
PCIe
message from
PCIe
5
SMI_STS.
PCI_EXP_SMI_ST
S
PCI_EXP_SMI_ST
S
None (enabled by
PCIe controller)
PCIe controller)
SMI
None
PMC_WAKE_PCIE
[3:0]# Assertion
[3:0]# Assertion
GPE0a_STS.PCIE_
WAKE[3:0]_STS
WAKE[3:0]_STS
GPE0a_STS.PCIE_
WAKE[3:0]_EN =
1b
WAKE[3:0]_EN =
1b
SCI
None
SCI
None
GPI[n]
10
ALT_GPIO_SMI.
CORE_GPIO_SMI_
STS[n]
STS[n]
2
or
ALT_GPIO_SMI.
ALT_GPIO_SMI.
SUS_GPIO_SMI_S
TS[n]
TS[n]
2
GPIO_ROUT[n]=0
1b
&
ALT_GPIO_SMI.
1b
&
ALT_GPIO_SMI.
CORE_GPIO_SMI
_EN[n]
_EN[n]
2
=1b
or
ALT_GPIO_SMI.
ALT_GPIO_SMI.
SUS_GPIO_SMI_E
N[n]
N[n]
2
=1b
SMI
None
USB Per-Port
Registers Write
Enable bit is
changed from 0b
to 1b
Registers Write
Enable bit is
changed from 0b
to 1b
UPRWC.WE_STS
&
SMI_STS.
&
SMI_STS.
USB_IS_STS
UPRWC.
WE_SMI_E=1b
&
SMI_EN.
&
SMI_EN.
USB_IS_SMI_EN
=1b
=1b
Sync SMI
6
None
Table 291. Causes of SMI and SCI (Sheet 3 of 3)
Event
Status
Indication
1
Enable
Condition
Interrupt Result
SMI_EN.
GBL_SMI_EN=1b
SMI_EN.
GBL_SMI_EN=0b
PM1_CNT
.SCI_EN=
1b
PM1_CNT
.SCI_EN=
0b
PM1_CNT.
SCI_EN=
1b
PM1_CNT.
SCI_EN=0
b