Intel E3815 FH8065301567411 Scheda Tecnica
Codici prodotto
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
4363
30.8.14
TCO1_CNT: TCO Timer Control (TCO1_CNT)—Offset 68h
Access Method
Default: 00000000h
Bit
Range
Default &
Access
Description
31:18
0b
RO
reserved (reserved2):
Reserved.
17
0b
RW
Second Timeout Status(SECOND_TO_STS) (second_to_sts):
PMC sets this bit to
1 to indicate that the TIMEOUT bit had been (or is currently) set and a second timeout
occurred before the TCO_RLD register was written. If this bit is set and the NO_REBOOT
config bit is 0, then the PMC will reboot the system after the second timeout. The reboot
is done by asserting PMU_PLTRST_B. This bit is only cleared by writing a 1 to this bit or
by a RSMRST_B.
16:4
0b
RO
reserved (reserved1):
Reserved.
3
0b
RW
TCO Timeout (TCO_TIMEOUT) (tco_timeout):
Bit set to 1 by PMC to indicate that
the SMI was caused by TCO timer reaching 0.
2:0
0b
RO
reserved:
Reserved.
Type:
I/O Register
(Size: 32 bits)
TCO1_CNT:
ACPI_BASE_ADDRESS Type:
PCI Configuration Register (Size:
32 bits)
ACPI_BASE_ADDRESS Reference:
ACPI_BASE_ADDRESS Reference:
[B:0, D:31, F:0] + 40h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
re
se
rv
ed
os_p
olicy
re
se
rv
ed
2
tco
_
lock
tc
o_tmr_halt
re
se
rv
ed
1
Bit
Range
Default &
Access
Description
31:22
0b
RO
reserved:
Reserved.
21:20
0b
RW
OS_POLICY (os_policy):
OS-based software writes to these bits to select the policy
that the BIOS will use after the platform resets due the WDT. The following convention is
recommended for the BIOS and OS: 00 Boot normally 01 Shut down 10 Dont load OS.
Hold in pre-boot state and use LAN to determine next step 11 Reserved
19:13
0b
RO
reserved (reserved2):
Reserved.
12
0b
RW
TCO Lock (TCO_LOCK) (tco_lock):
When set to 1, this bit prevents writes from
changing the TCO_EN bit (in offset 30h of Power Management I/O space). Once this bit
is set to 1, it can not be cleared by software writing a 0 to this bit location. A core-well
reset is required to change this bit from 1 to 0. This bit defaults to 0.
11
0b
RW
TCO Timer Halt (TCO_TMR_HALT) (tco_tmr_halt):
1 = The TCO timer will halt. It
will not count, and thus cannot reach a value that would cause an SMI# or to cause the
SECOND_TO_STS bit to be set. This will also prevent rebooting. 0 = The TCO timer is
enabled to count. This is the default.