Intel E3815 FH8065301567411 Scheda Tecnica
Codici prodotto
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
5300
Datasheet
42.3.2
MICW2—Offset 21h
Master ICW2 is used to initialize the interrupt controller with the five most significant
bits of the interrupt vector address. The value programmed for bits[7:3] is used by the
CPU to define the base address in the interrupt vector table for the interrupt routines
associated with each IRQ on the controller. Typical ISA ICW2 values are 08h for the
master controller and 70h for the slave controller.
Access Method
Default: 00h
42.3.3
MOCW2—Offset 24h
Master Operational Control Word 2 (Interrupt Mask).Following a part reset or ICW
initialization, the controller enters the fully nested mode of operation. Non-specific EOI
without rotation is the default. Both rotation mode and specific EOI mode are disabled
following initialization.
Access Method
4
X
WO
ICWOCWSEL:
ICW/OCW select: This bit must be a 1 to select ICW1 and enable the
ICW2, ICW3, and ICW4 sequence.
3
X
WO
LTIM:
Edge/Level Bank Select (LTIM): Disabled. Replaced by ELCR1 and ELCR2.
2
X
WO
ADI:
ADI. Ignored for VLV. Should be programmed to 0.
1
X
WO
SNGL:
Single or Cascade (SNGL): Must be programmed to a 0 to indicate two
controllers operating in cascade mode.
0
X
WO
IC4:
wICW4 Write Required (IC4): This bit must be programmed to a 1 to indicate that
ICW4 needs to be programmed.
Bit
Range
Default &
Access
Description
Type:
I/O Register
(Size: 8 bits)
MICW2:
7
4
0
0
0
0
0
0
0
0
0
IVBA
IRL
Bit
Range
Default &
Access
Description
7:3
X
WO
IVBA:
Interrupt Vector Base Address: Bits [7:3] define the base address in the interrupt
vector table for the interrupt routines associated with each interrupt request level input.
2:0
X
WO
IRL:
Interrupt Request Level: When writing ICW2, these bits should all be 0. During an
interrupt acknowledge cycle, these bits are programmed by the interrupt controller with
the interrupt to be serviced. This is combined with bits [7:3] to form the interrupt vector
driven onto the data bus during the second INTA# cycle. The code is a three bit binary
code: Code Master Interrupt Slave Interrupt 000 IRQ0 IRQ8 001 IRQ1 IRQ9 010 IRQ2
IRQ10 011 IRQ3 IRQ11 100 IRQ4 IRQ12 101 IRQ5 IRQ13 110 IRQ6 IRQ14 111 IRQ7
IRQ15
Type:
I/O Register
(Size: 8 bits)
MOCW2: