Intel E3815 FH8065301567411 Scheda Tecnica
Codici prodotto
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
884
Datasheet
14.11.211 DSPACNTR—Offset 70180h
Display A Plane Control Register
Access Method
Default: 00000000h
11:4
0b
RW
RESERVED:
MBZ
3
0b
RW
FLIP_SOURCE:
Project:
All
Default Value:
0b
This bit indicates if the source of the flip is CS or BCS so display can send the flip done
response to the appropriate destination.
ValueNameDescriptionProject
0b
CS
Flip source is CS
All
1b
BCS
Flip source is BCS
All
2
0b
RW
DECRYPTION_REQUEST:
Project:
All
Default Value:
0b
This bit requests decryption to be enabled for this plane. This request will be qualified
with the separate decryption allow message in order to create the decryption enable.
This bit is only allowed to change on a synchronous flip, but once set with a synchronous
flip, the bit can remain set while using asynchronous flips. This value is loaded into the
surface base address register of the associated plane. Usage must conform to the rules
outlined in the plane surface base address register.
1:0
0b
RW
RESERVED_1:
MBZ
Bit
Range
Default &
Access
Field Name (ID): Description
Type:
Memory Mapped I/O Register
(Size: 32 bits)
Offset:
GTTMMADR_LSB Type:
PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference:
GTTMMADR_LSB Reference:
[B:0, D:2, F:0] + 10h