Texas TMS320C645X Manuale Utente
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5.45
LSUn Control Register 4 (LSUn_REG4)
SRIO Registers
There are four of these registers, one for each LSU.
Figure 101. LSUn Control Register 4 (LSUn_REG4)
31-30
29-28
27-26
25-24
23-16
OUTPORTID
PRIORITY
XAMBS
ID_SIZE
DESTID
RW-0x00
RW-0x00
RW-0x00
RW-0x00
RW-0x00
LEGEND: R = Read only; -n = value after reset
15-8
7-1
0
DESTID
Reserved
INTER
RUPT
_REQ
_REQ
RW-0x00
R-0x00
RW-
0x00
LEGEND: R = Read only; -n = value after reset
Table 75. LSUn Control Register 4 (LSUn_REG4) Field Descriptions
Bit
Field
Value
Description
31-30
OUTPORTID
Not applicable for Rapid IO header. Indicates the output port number for the packet to be
transmitted from. Specified by the CPU along with NodeID.
transmitted from. Specified by the CPU along with NodeID.
29-28
PRIORITY
RapidIO prio field specifying packet priority. Request packets should not be sent at a priority level of
3 in order to avoid system deadlock. It is the responsibility of the software to assign the appropriate
outgoing priority.
3 in order to avoid system deadlock. It is the responsibility of the software to assign the appropriate
outgoing priority.
27-26
XAMBS
RapidIO xambs field specifying extended address MSB
25-24
ID_SIZE
RapidIO tt field specifying 8 or 16bit DeviceIDs
00b
8 bit device Ids
01b
16 bit device Ids
23-8
DESTID
RapidIO destinationID field specifying target device
7-1
Reserved
Reserved
0
INTERRUPT_RE
CPU controlled request bit used for interrupt generation. Typically used in conjunction with
Q
Non-posted commands to alert the CPU when the requested data/status is present.
0b
Interrupt is not requested upon completion of command
1b
Interrupt is requested upon completion of command
Serial RapidIO (SRIO)
146
SPRU976 – March 2006