Biostar U8668-D BIOS Manuale Proprietario
BIOS Setup
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When Enabled, writes to the PCI bus are executed with zero-wait
states.
states.
The Choices: Enabled (default), Disabled.
PCI Delay Transaction
The chipset has an embedded 32-bit posted write buffer to support
delay transactions cycles. Select Enabled to support compliance with
delay transactions cycles. Select Enabled to support compliance with
PCI specification.
The Choices: Disabled, Enabled (default).
Memory Hole
When enabled, you can reserve an area of system memory for ISA adapter
ROM. When this area is reserved , it cannot be cached. Refer to the user
ROM. When this area is reserved , it cannot be cached. Refer to the user
documentation of the peripheral you are installing for more information.
The Choices: Disabled (default), 15M – 16M.
The Choices: Disabled (default), 15M – 16M.
System BIOS Cacheable
Selecting the “Enabled” option allows caching of the system BIOS ROM at
F0000h-FFFFFh which can improve system performance. However, any
programs writing to this area of memory will cause conflicts and result in system
errors.
The Choices: Enabled, Disabled (default).
F0000h-FFFFFh which can improve system performance. However, any
programs writing to this area of memory will cause conflicts and result in system
errors.
The Choices: Enabled, Disabled (default).
Delay Prior to Thermal
The time periods would correspond to the amount of time required to boot
various supported configurations. Example selections include 4, 8, 16, 32
minutes. The watchdog timer would generate an SMI, presenting the BIOS an
opportunity to enable the TCC in non-ACPI compliant operating systems.
The Choices: 16Min (default), 4Min, 8Min, 32Min.
various supported configurations. Example selections include 4, 8, 16, 32
minutes. The watchdog timer would generate an SMI, presenting the BIOS an
opportunity to enable the TCC in non-ACPI compliant operating systems.
The Choices: 16Min (default), 4Min, 8Min, 32Min.
VGA Share Memory Size
This item allows you to select the VGA share memory size.
The Choices: 32M (default), 8M, 16M, Disabled.
The Choices: 32M (default), 8M, 16M, Disabled.
FB Address Conversion
Setting this bit further optimizes the MA table for VGA frame buffer accesses
according to the DRAM page size in use. Setting this should improve VGA
performance especially in tiling address mode. This but cannot be used the
same time as CPU Direct Access FB mode. If used, this bit must be set before
enabling the internal VGA to prevent display corruption.
The Choices: Enabled (default), Disabled.
according to the DRAM page size in use. Setting this should improve VGA
performance especially in tiling address mode. This but cannot be used the
same time as CPU Direct Access FB mode. If used, this bit must be set before
enabling the internal VGA to prevent display corruption.
The Choices: Enabled (default), Disabled.