Rockwell SoniCrafter BT8960 Manuale Utente

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3.0  Registers
 
3.1  Conventions
Bt8960
Single-Chip 2B1Q Transceiver
 N8960DSB
3.2.65   0x79—Equalizer Write Select Register (eq_add_write)
A 6-bit read/write register representing an unsigned binary address defined over a range of 0 to 47 decimals.
When written, it causes the lowest-order 16 bits of the Access Data Register [access_data_byte[3:0]; 0x7C–
0x7F] to be subsequently written to the selected equalizer register file location within two symbol periods. Does
not affect the value of the access data register. An address map of the shared register file, as defined by the fac-
tory-delivered microcode, is shown below. 
3.2.66   0x7A—Equalizer Microcode Read Select Register (eq_microcode_add_read)
A 6-bit read/write register representing an unsigned binary address defined over a range of 0 to 63 decimals.
When written, it causes the selected 32-bit location of the equalizer microprogram store to be subsequently
loaded into the Access Data Register [access_data_byte[3:0]; 0x7C–0x7F] within two symbol periods. Does not
affect the value of the microprogram store location. 
3.2.67   0x7B—Equalizer Microcode Write Select Register 
(eq_microcode_add_write)
A 6-bit read/write register representing an unsigned binary address defined over a range of 0 to 63 decimals.
When written, it causes all 32 bits of the Access Data Register [access_data_byte[3:0]; 0x7C–0x7F] to be sub-
sequently written to the selected equalizer microprogram store location within two symbol periods. Does not
affect the value of the access data register. Factory-developed equalizer microcode is included with the no-fee
licensed HDSL transceiver software available from Rockwell. 
3.2.68   0x7C–0x7F—Access Data Register (access_data_byte3:0)
A 4-byte read/write register stores filter coefficient, equalizer register file, and equalizer microprogram store
contents during indirect accesses to these RAM-based locations. Writes to addresses 0x70 through 0x7B, utilize
the contents of this shared register as specified in each of the individual register descriptions.
7
6
5
4
3
2
1
0
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
7
6
5
4
3
2
1
0
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
7
6
5
4
3
2
1
0
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]