Renesas Stereo System SH7709S Manuale Utente
Rev. 5.00, 09/03, page 169 of 760
Bit 31—BRDR Valid Flag (DVF): Indicates whether a branch destination address is stored.
When a branch destination address is fetched, this flag is set to 1. This flag is set to 0 in reading
BRDR.
When a branch destination address is fetched, this flag is set to 1. This flag is set to 0 in reading
BRDR.
Bit 31: DVF
Description
0
The value of BRDR register is invalid
1
The value of BRDR register is valid
Bits 30 to 28—Reserved: These bits are always read as 0. The write value should always be 0.
Bits 27 to 0—Branch Destination Address (BDA27 to BDA0): These bits store the first fetched
address after branch.
address after branch.
7.2.13
Break ASID Register A (BASRA)
Break ASID register A (BASRA) is an 8-bit read/write register that specifies the ASID that serves
as the break condition for channel A. It is not initialized by resets.
as the break condition for channel A. It is not initialized by resets.
Bit:
7
6
5
4
3
2
1
0
BASA7
BASA6
BASA5
BASA4
BASA3
BASA2
BASA1
BASA0
Initial value:
*
*
*
*
*
*
*
*
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Note:
*
Undefined value
Bits 7 to 0—Break ASID A7 to 0 (BASA7 to BASA0): These bits store the ASID (bits 7 to 0)
that is the channel A break condition.
that is the channel A break condition.
7.2.14
Break ASID Register B (BASRB)
Break ASID register B (BASRB) is an 8-bit read/write register that specifies the ASID that serves
as the break condition for channel B. It is not initialized by resets.
as the break condition for channel B. It is not initialized by resets.
Bit:
7
6
5
4
3
2
1
0
BASB7
BASB6
BASB5
BASB4
BASB3
BASB2
BASB1
BASB0
Initial value:
*
*
*
*
*
*
*
*
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Note:
*
Undefined value
Bits 7 to 0—Break ASID A7 to 0 (BASB7 to BASB0): These bits store the ASID (bits 7 to 0)
that is the channel B break condition.
that is the channel B break condition.