Oracle Vacuum Cleaner CPU-56T Manuale Utente

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Installation
Hardware  Accessories
40
SPARC/CPU−56T
PMC#4
PMC#3
PMC#2
PMC slot 2 supports a 64−bit data bus width with a maximum frequency of 33 MHz and
is attached to PCI bus B. PMC slots 3 and 4 support a 64−bit data bus width with a
maximum frequency of 66 MHz and are attached to PCI bus C.
a
If a 32−bit PMC module is mounted into PMC slots 3 and 4, the Sentinel64 PCI−to−PCI
bridge dynamically detects the 32−bit bus and changes its transfer size to 32−bit for this
PMC module. If a 64−bit PMC module is mounted into PMC slots 3 and 4, burst transfers
between all 64−bit PCI devices on PCI bus B and C will be 64−bit PCI transfers.
Note:
a
If a 33−MHz PMC module is mounted into PMC slots 3 and 4, the whole PCI bus
C will run with 33 MHz only. This may result in performance degradation.
The signaling level of each PMC slot is determined via a voltage key which has to be
installed into one of two holes that belong to each PMC slot. One hole corresponds to a
signalling level of 5V, the other to a signaling level of 3.3V. Depending on the hole the
voltage key is installed into, the signaling level is set accordingly. This is illustrated in the
figure below.
a
5V
3.3V
Figure 2:
 Location of PMC Voltage Keys
By default, PMC slots 3 and 4 have a signaling level of 3.3V and PMC slot 2 has a
signaling level of 5V. A description of how to change the signalling level for a PMC slot is
given in the following installation procedure.
a
Note:
a
A 66−MHz PCI bus configuration requires that the signaling level and therefore
the VI/O voltage is 3.3 V.