Oracle Vacuum Cleaner CPU-56T Manuale Utente

The EBus is a generic slave 8−bit wide Direct Memory Access (DMA) bus (pseudo ISA
bus) to which the following devices are connected:

S Field−Programmable Gate Array (FPGA)

S PLCC PROM and flash memory device

S Real time clock and NVRAM

S Quad serial controller

The used FPGA is a Spartan XCS20XL device made by XILINX. It provides the following
main features:

S Watchdog

S Timer

S Temperature sensor control

S Two local I

2

C interfaces

S Ethernet interface 1/3 switching

S LED and switch control

S Reset control

The CPU board

′s watchdog is implemented inside the FPGA. It is used to reset the board

after a configured time, if no software trigger occurred. If enabled in the Interrupt Enable
Control register, an interrupt will be generated before the watchdog timer runs out.

a

The watchdog can be enabled by setting SW1−3 to ON. It starts with the first trigger of the
watchdog trigger bit in the Watchdog Trigger register. After the watchdog was started, it
is not possible to stop it anymore.

a

The Watchdog Timer Control Register allows to specify the time after which an interrupt
is generated and after which a reset is issued. For both, values between 125 ms up to 1
hour in 15 steps are possible. The value of each following step is increased by a factor of
between 1.5 and 3. To be compatible to the predecessor board SPARC/CPU−54, the time
after which a reset is issued after a reset is set to 2.5 s and the time after which an