Nortel Networks Video Gaming Accessories 553-3001-211 Manuale Utente

 NTAK93 D-channel Handler Interface daughterboard

A Z80A-DMA chip controls the data transfer between local RAM memory 
and communication ports. The DMA channels are only used in the receive 
direction (from line to SSC), not in the transmit direction.

A total of 32 kBytes of RAM space for each pair of ports is used as the 
communication buffer and for firmware data storage.

A total of 32K bytes of ROM space for each pair of ports is reserved as a code 
section of the DCH-PORT firmware.

One chip controls each pair of independent communication ports. It performs 
the functions of serial-to-parallel and parallel-to-serial conversions, error 
detection, and frame recognition (in HDLC). The parameters of these 
functions are supplied by the DCH-PORT firmware.

Two chips are used as real-time timers and baud-rate generators for each pair 
of communication ports.

This portion of the circuit handles address/data bus multiplexing, the 
interchange of data, commands, and status between the on board processors 
and software. It includes transmit buffer, receive buffer, command register, 
and status register for each communication channel.

The mode of operation of the DCH-PORT is controlled by a switch setting on 
the NTAK09/NTBK50. For DPNSS the switch is ON; for DCHI it is OFF.