NEC EXPRESS 5800 Manuale Utente
Product Guide – NEC Express5800/120Rd-1
October 2003
October 2003
6
KEY PRODUCT FEATURES & USER BENEFITS
Next-generation Xeon Processing and Enhanced System Architecture
NEC Express5800/120Rd-1 is built to take full advantage of the latest Xeon processors
2.4BGHz with 512KB cache, 3.06GHz with 512KB cache and 3.20GHz with 1MB cache.
These processors are packaged in the new FC-mPGA2 form factor, a 603-pin socket version of
the Xeon.
The design of NEC Express5800/120Rd-1 is built upon a 533MHz Front Side Bus (FSB), the
E7501 chipset from Intel and DDR266 SDRAM memory. The Intel Xeon processor for dual-
processing servers offers users several new system performance boosts, with Hyper-Threading
technology and the E7501 server chipset.
The Intel E7501 chipset supports DDR memory technology and is optimized for the Intel Xeon
processor. The new chipset will accelerate memory access to increase platform performance and
deliver new levels of performance for I/O intensive server applications.
This chipset also allows increased throughput and enhanced overall system performance
through the high-performance 533MHz FSB and full-speed 266MHz memory access.
2.4BGHz with 512KB cache, 3.06GHz with 512KB cache and 3.20GHz with 1MB cache.
These processors are packaged in the new FC-mPGA2 form factor, a 603-pin socket version of
the Xeon.
The design of NEC Express5800/120Rd-1 is built upon a 533MHz Front Side Bus (FSB), the
E7501 chipset from Intel and DDR266 SDRAM memory. The Intel Xeon processor for dual-
processing servers offers users several new system performance boosts, with Hyper-Threading
technology and the E7501 server chipset.
The Intel E7501 chipset supports DDR memory technology and is optimized for the Intel Xeon
processor. The new chipset will accelerate memory access to increase platform performance and
deliver new levels of performance for I/O intensive server applications.
This chipset also allows increased throughput and enhanced overall system performance
through the high-performance 533MHz FSB and full-speed 266MHz memory access.
The I/O subsystem of NEC Express5800/120Rd-1 is built on a 3 peer PCI bus architecture that
provides concurrency of data transfers between the different high speed I/O channels and CPU
or memory. I/O traffic is balanced as follows:
provides concurrency of data transfers between the different high speed I/O channels and CPU
or memory. I/O traffic is balanced as follows:
- First PCI bus (32-bit): ATA-100 controller, IDE, graphics and I/O ports
- Second PCI bus (64-bit): dual-port LAN and 1x 64-bit PCI slots
- Second PCI bus (64-bit): dual-port LAN and 1x 64-bit PCI slots
- Third PCI bus (64-bit): Ultra 320 SCSI channels and 1x 64-bit PCI slots
Improved Memory Architecture
NEC Express5800/120Rd-1 offers 6 DIMM sockets for industry-standard 128MB, 256MB,
512MB, 1GB or 2GB SDRAM DDR266 DIMM. NEC Express5800/120Rd-1 allows easy
expansion of system’s capabilities to memory-intensive environments (scalability up to 12GB)
and comes standard with 9-bit parity/ECC 266MHz SDRAM for maximum data integrity.
The memory controller supports memory scrubbing, single-bit error correction and multiple-
bit error detection and chip kill is supported. Memory can be implemented with either single
sided (one row) or double-sided (two row) DIMMs.
512MB, 1GB or 2GB SDRAM DDR266 DIMM. NEC Express5800/120Rd-1 allows easy
expansion of system’s capabilities to memory-intensive environments (scalability up to 12GB)
and comes standard with 9-bit parity/ECC 266MHz SDRAM for maximum data integrity.
The memory controller supports memory scrubbing, single-bit error correction and multiple-
bit error detection and chip kill is supported. Memory can be implemented with either single
sided (one row) or double-sided (two row) DIMMs.
Chipkill Correct Memory
NEC Express5800/120Rd-1 supports Chipkill Correct Memory architecture. Chipkill gives
the memory system the ability to withstand a multibit failure within a DRAM device,
including a failure that causes incorrect data on all data bits of the device.
the memory system the ability to withstand a multibit failure within a DRAM device,
including a failure that causes incorrect data on all data bits of the device.