Connect Tech CANPRO CTIM-00043 Manuale Utente
CANpro/104 User Manual
CTIM-00043 (0.01) 1/15/2010
www.connecttech.com
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800-426-8979 | 519-836-1291
Hardware Installation – Rev C & Later
The Connect Tech CANpro/104 board provides two (2) industry standard SJA1000 CAN Bus controllers in
a PC/104 board format which supports both I/O and Memory mapping configurability.
All the configuration options are setup with jumpers, identified as J1, J2, J3A, J3B, J3C, J4 and J5.
Jumpers are always oriented as indicated in the drawing below.
a PC/104 board format which supports both I/O and Memory mapping configurability.
All the configuration options are setup with jumpers, identified as J1, J2, J3A, J3B, J3C, J4 and J5.
Jumpers are always oriented as indicated in the drawing below.
The jumper positions are numbered on the PCB (and are shown in the above drawing). J1 and J2 are
Interrupt Selection jumpers, and the numbers (3, 4, 5, 6, 7, 9, 10, 11, 12, 14 and 15) refer to the actual
interrupt number being selected. J3A, J3B and J3C positions are numbered sequentially from left to right.
J3A and J3C have 6 positions, J3B has 7 positions. J4 and J5 positions are labeled “T” and “G”.
Interrupt Selection jumpers, and the numbers (3, 4, 5, 6, 7, 9, 10, 11, 12, 14 and 15) refer to the actual
interrupt number being selected. J3A, J3B and J3C positions are numbered sequentially from left to right.
J3A and J3C have 6 positions, J3B has 7 positions. J4 and J5 positions are labeled “T” and “G”.
Memory vs I/O Spaces
The first decision to make when configuring this board, it to select whether the board will operate within the
Memory or I/O address Space of the computer system in which the board is installed. First a quick
description of the two different Spaces.
Memory or I/O address Space of the computer system in which the board is installed. First a quick
description of the two different Spaces.
Memory Space
Most (but not all) PC/104 CPU System board vendors provide one or more regions of Memory
Addresses that can be configured (or allocated) to the PC/104 Expansion bus connector(s) on CPU
System board. This setup may be performed via the BIOS setup or via jumpers or switches on the
System board. This memory region is usually located at addresses below the 1-Meg CPU memory
address (commonly referred to as the Upper Memory addresses), although some System boards
allow the PC/104 Expansion Bus to be allocated to blocks of addresses within the first 16-Meg of
memory.
Addresses that can be configured (or allocated) to the PC/104 Expansion bus connector(s) on CPU
System board. This setup may be performed via the BIOS setup or via jumpers or switches on the
System board. This memory region is usually located at addresses below the 1-Meg CPU memory
address (commonly referred to as the Upper Memory addresses), although some System boards
allow the PC/104 Expansion Bus to be allocated to blocks of addresses within the first 16-Meg of
memory.