Arm Enterprises GP4020 Manuale Utente
12: Peripheral Control Logic
114
GP4020 GPS Baseband Processor Design Manual
PL
LD
T
1
UA
RT
_C
LK
B
uIL
D_
CL
K
R
F
_P
LL_LO
C
K
RT
C_
CL
K
N
S
R
ESET
P
O
W
E
R
_GOOD
EN
_P
O
W
_R
ST
F
_SL
EEP
SF
T
_R
ESET
UA
RT
_C
LK
N
R
ESET
(T
O
F
IRE
F
LY
, CO
RR)
N
P
O
R
_R
ESET
(T
O
1
PPS, R
T
C
, SC
G
)
P
O
W
_CNT
L
R
E
G
IST
ER
U
IM
AD
D
R
ESS & D
A
T
A
BU
S
UIM
B
U
S
IO
_R
EV
R
E
G
IST
ER
IP_
R
EAD
R
E
G
IST
ER
PER
_S
T
A
T
[1
3:
0]
RE
G
IS
T
E
R
N
S
R
S
T
_R
ESET
W
A
T
_R
ESET
PO
W
_R
ESET
PL
L_
R
ESET
SF
T
_R
ESET
CL
R_
RS
T
EN
_P
O
W
_R
ST
E
N
_P
LL_R
S
T
PL
L_
IN_
SEL
[1
:0
]
PL
L_
BYP
B_
C
LK_
SEL
[1
:0
]
F
_SL
EEP
PL
L_
S
LEEP
R
F
_S
LE
E
P
W
A
K
_UA
RT
W
AK_
C
O
R
W
AK_
D
ISC
W
A
T
CH_
E
N
PO
W
G
_E
N
DISCIO
_C
F
G
[2
:0
]
M
F
NIO
_CF
G
[2
:0
]
DIS
C
O
P
_M
UX
BSIO
_M
U
X[1
:0
]
EXT
_N
C
S
0
IO_R
EV[
15:10]
CHI
P
_RE
V
[5
:0
]
T
EST
M
O
D
E
SIG
N
0
MA
G
0
T
IME
MA
R
K
TI
C
M
U
LT
I_
F
N
IO
_R
EAD
P
O
W
E
R
_GOOD
D
ISC
IO
_R
EAD
DIS
C
O
P
PER
_I
N
T
R
F
_P
LL_LO
C
K
RT
C_
CM
P
_INT
PO
W
_G
D
_I
N
T
TI
C
_I
N
T
CL
R_
INT
R
C
M
P_
IN
T
_EN
PO
W
_IN
T
_EN
E
N
_P
LL_R
S
T
PL
L_
IN_
SEL
[1
:0
]
PL
L_
SL
EEP
PL
L_
EN
ABL
E
R
ESET
LOGI
C
M
U
LT
IP
LE
X
LOGI
C
UA
RT
_C
LK
MU
LT
I_
F
N
IO
M
U
LT
I_
F
N
IO
_R
EAD
G
P
IO
[0
:7
]
C
LK1
00
KH
z
G
P
IO
[0
:7
]
BSIO
TI
C
RF
_P
D
W
A
T
CH_
T
M
W
A
T
CH_
E
N
DISCIO
_C
F
G
[2
:0
]
M
F
NIO
_CF
G
[2
:0
]
DIS
C
O
P
_M
UX
BSIO
_M
U
X[1
:0
]
UA
RT
_C
LK
BSIO
DIS
C
IP
1
DIS
C
IO
D
ISC
IO
_R
EAD
W
A
T
CH_
E
N
IN
T
E
RRUP
T
AN
D
W
AKE-
U
P
LOGI
C
W
A
T
CH_
INT
M
EAS_
IN
T
A
CCUM
_I
NT
UA
RT
_I
NT
RT
C_
CM
P
_INT
P
O
W
E
R
_GOOD
TI
C
_I
N
T
DIS
C
IP
1
N
R
ESET
W
AK_
C
O
R
W
A
K
_UA
RT
R
C
M
P_
IN
T
_EN
PO
W
_IN
T
_EN
W
AK_
D
ISC
PER
_I
N
T
N
S
LP
_R
ESET
R
F
_S
LE
E
P
PL
L_
PD
PL
L_
IN_
SEL
[1
:0
]
PL
L_
BYP
B_
C
LK_
SEL
[1
:0
]
P
LL_E
N
A
B
LE
RF
_P
D
R
F
_S
LE
E
P
P
LL_P
D
PL
L_
S
LEEP
N
S
R
S
T
_R
ESET
W
A
T
_R
ESET
PO
W
_R
ESET
PL
L_
R
ESET
CL
R_
RS
T
RT
C_
CM
P
_INT
PO
W
_G
D
_I
N
T
TI
C
_I
N
T
P
O
W
E
R
_GOOD
RF
_P
D
PR
X_
EN
P
LL_P
D
C
L
R
_
SL
EEP
N
S
LP
_R
ESET
G
P
IO
[0
:7
]
G
P
IO
[0
:7
]
DIS
C
O
P
T
EST
T
EST
M
O
D
E
U
IM
_T
EST
U
IM
_T
EST
SIG
N
1
MA
G
1
INT
_NCS
0
INT
_NCS
0
EXT
_N
C
S
0
INT
_NCS
0
C
L
R
_
R
ESET
CL
R_
INT
CL
R_
IN
T
E
RRUP
T
CL
R_
RS
T
"P
O
W
E
R
CO
NT
RO
L"
LI
N
ES T
O
SC
G
P
O
W
E
R
_GOOD
PO
W
G
_E
N
RF
_P
DO
W
N
P
LL_P
D
O
WN
PR
X_
PD
O
W
N
PR
X_
EN
Figure 12.1 Peripheral Control Logic Top-level Block Diagram
•
NSRESET (Pin 75 (100-pin package)). This indicates that a RESET has been requested from an external
source, perhaps a Reset Button. A system reset will occur as shown in Figure 12.6 on page 117, if this pin is
taken Low (i.e. '0'). This is the only reset source by which ALL GP4020 registers, which can be reset, are
completely reset (except for the Data Retention Register in TIC_RET within the 1PPS Timemark Generator, and
the Real Time Clock Counters). An active Low pulse of greater than 10ns is required on this pin in order to
guarantee that a reset occurs. The NSRESET pin is the only hardware-reset source that can reset the
PER_STAT [4:0] register bits, used to indicate sources of reset.
source, perhaps a Reset Button. A system reset will occur as shown in Figure 12.6 on page 117, if this pin is
taken Low (i.e. '0'). This is the only reset source by which ALL GP4020 registers, which can be reset, are
completely reset (except for the Data Retention Register in TIC_RET within the 1PPS Timemark Generator, and
the Real Time Clock Counters). An active Low pulse of greater than 10ns is required on this pin in order to
guarantee that a reset occurs. The NSRESET pin is the only hardware-reset source that can reset the
PER_STAT [4:0] register bits, used to indicate sources of reset.