Arm Enterprises GP4020 Manuale Utente
12: Peripheral Control Logic
GP4020 GPS Baseband Processor Design Manual
129
Bit
No.
Mnemonic
Description
Reset
Value
Value
R/W
13
POW_INT_EN
Enable PER_INT Interrupt signal to Interrupt Controller in Firefly MF1, due
to POW_GD_INT (POWER_GOOD (pin 64) going Low.)
'1' = Enable Interrupt due to POWER_GOOD Low
'0' = Disable
to POW_GD_INT (POWER_GOOD (pin 64) going Low.)
'1' = Enable Interrupt due to POWER_GOOD Low
'0' = Disable
0
R/W
12
RCMP_INT_EN
Enable PER_INT Interrupt signal to Interrupt Controller in Firefly MF1, due
to RTC_CMP_INT signal from Real Time Clock.
'1' = Enable Interrupt due to RTC_CMP_INT High.
'0' = Disable
to RTC_CMP_INT signal from Real Time Clock.
'1' = Enable Interrupt due to RTC_CMP_INT High.
'0' = Disable
0
R/W
11
CLR_INT
Write: '1' = No effect.
Write: '0' = Reset PER_STAT[10:8] after next UART_CLK cycle (i.e. Reset
Write: '0' = Reset PER_STAT[10:8] after next UART_CLK cycle (i.e. Reset
ALL Interrupt Read bits).
Read: always '1'
1
R/W
10
TIC_INT
(See Note1)
(See Note1)
TIC_INT Interrupt status from 1PPS Timemark Generator.
'1' = TIC period correction required / about to occur. (This bit will be set
'1' = TIC period correction required / about to occur. (This bit will be set
even if TIC_INT is disabled by PER_STAT[15:14]).
‘0’ = No TIC period correction required / about to occur.
0
R/W
9
POW_GD_INT
(See Note1)
POW_GD_INT Interrupt status from POWER_GOOD input (pin 64 (100-pin
package)).
package)).
'1' = PER_INT Interrupt due to POWER_GOOD Low. (This bit will be set
only if POW_INT_EN (PERSTAT[13]) is Enabled.)
‘0’ = No PER_INT interrupt due to POWER_GOOD.
0
R
8
RTC_CMP_INT
(See Note1)
(See Note1)
RTC_CMP_INT Interrupt status from Real Time Clock.
'1' = PER_INT Interrupt due to RTC counters equal to RTC Comparison
'1' = PER_INT Interrupt due to RTC counters equal to RTC Comparison
Registers. (This bit will be set only if RCMP_INT_EN
(PER_STAT[12]) is Enabled.
(PER_STAT[12]) is Enabled.
‘0’ = No PER_INT interrupt due to RTC.
0
R
7
EN_PLL_RST
Reset of Firefly and Correlator due to RF_PLL_LOCK (pin 56 (100-pin
package)) going Low.
'1' = Enabled
‘0’ = Disabled
package)) going Low.
'1' = Enabled
‘0’ = Disabled
Note: This should only be disabled if UART_CLK and B
µ
ILD_CLK are NOT
derived from M_CLK in the SCG block.
1
R/W
6
EN_POW_RST
Reset of Firefly and Correlator due to POWER_GOOD (pin 64 (100-pin
package)) going Low.
'1' = Enabled
‘0’ = Disabled
package)) going Low.
'1' = Enabled
‘0’ = Disabled
1
R/W
5
CLR_RST
Write: '1' = No effect.
Write: '0' = Reset PER_STAT[4:0] after next UART_CLK cycle (i.e. Reset
Write: '0' = Reset PER_STAT[4:0] after next UART_CLK cycle (i.e. Reset
ALL "Reset-Source" Read bits).
Read: always '1'
1
R/W
4
SFT_RESET
(See Note 2)
Software triggered Reset of Hardware.
Write '1' = No effect.
Write '0' = Reset of Firefly and Correlator at next UART_CLK cycle.
Write '1' = No effect.
Write '0' = Reset of Firefly and Correlator at next UART_CLK cycle.
Read '1' = Reset due to SFT_RESET (writing '0' to this bit), has occurred
since last CLR_INT or NSRESET clear-event.
Rd: 0
Wr: 1
Wr: 1
R/W
3
PLL_RESET
(See Note 2)
'1' = Reset due to RF_PLL_LOCK = Low, has occurred since last CLR_RST
or NSRESET clear-event.
‘0’ = No reset event due to RF_PLL_LOCK has occurred
0
R