Arm Enterprises GP4020 Manuale Utente
1: Introduction
8
GP4020 GPS Baseband Processor Design Manual
1.4 Typical
Application
ANT
E
NNA
470
470
1k
SAM
PC
LK
SIG
N
0
MA
G
0
(58)
(59)
(61)
(62)
(63)
(64)
(56)
GP
4020
(84)
Bu
IL
D
_C
LK
M_CLK
P
O
W
E
R
_GOOD
R
F
_P
LL_LO
C
K
SAM
PC
LK
SIG
N
0
MA
G
0
CL
K
_I
CL
K
_T
B
OOT
R
O
M
S
RAM
(2K
X
32)
FI
R
E
FLY
M
F
1
M
ICRO
CO
NT
RO
L
L
E
R
UA
RT
1
ARM
7T
DM
I
FLA
S
H
EPR
O
M
(16-B
IT
)
ST
A
T
IC
RAM
(16-B
IT
)
1
PPS
G
E
NE
RAT
O
R
WAT
CHDO
G
BS
IO
3
-WIRE
SER
IA
L
INT
E
RF
ACE
UART
2
G
E
NE
RAL
PU
R
P
O
SE I
O
(8
L
IN
ES)
IC
E
NICE
IN
T
E
RRUP
T
CO
NT
RO
LL
E
R
DM
A
CO
NT
RO
LL
E
R
TI
M
E
R
/
CO
UNT
E
R
(x
2)
RE
AL
T
IM
E
CL
O
C
K
ME
MO
R
Y
P
E
R
IP
HE
RA
L
CO
NT
RO
LL
E
R
N
S
R
ESET
SER
IAL
C
O
M
M
S
PO
R
T
2
G
P
IO
/ BSIO
JT
AG IN
TE
RF
ACE
SYST
EM
C
L
O
C
K
G
E
NE
RAT
O
R
WI
T
H
P
L
L
R
ESET
L
OGIC
1
2
CHANNE
L
CO
RRE
L
A
T
O
R
22k
SYST
EM
SER
VIC
E
S
(75)
1
PU
L
SE PER
SEC
O
N
D
32
kHz
Cr
ys
ta
l
T
EST
IDDQ
T
E
S
T
(67)
(70)
T
IME
MA
R
K
(69)
RA
W
T
IME
MA
R
K
SER
IAL
C
O
M
M
S
PO
R
T
1
10M
10pF
10pF
(72)
(73)
RT
C_
XIN
RT
C_
XO
U
T
100k
100k
100k
10nF
100k
10nF
(17)
(16)
22k
Mai
n +
3.3V
G
P
2015
35M
H
z
SAW
FI
LTE
R
175M
H
z
LC
FI
LTE
R
LD
CL
K
MA
G
SIG
N
OP
C
LK
+
OP
C
LK
-
(15)
(14)
(11)
(21)
PR
EF
(8
)
1575M
H
z
RF
FI
LTE
R
R
ESET
G
E
NE
RAT
O
R
(e.g
D
S
1818-5)
10M
H
z
TC
X
O
10k
G
P
4020 +
3.3V
Mai
n +
3.3V
Figure 1.2 Block Diagram of typical GP4020 based GPS receiver