Arm Enterprises GP4020 Manuale Utente
14: System Clock Generator
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GP4020 GPS Baseband Processor Design Manual
Figure 14.5 GP4020 System Clock Generator PLL Configuration
The PLL can provide accurate phase alignment between a generated clock and a reference clock without incurring
delays normally associated with buffering. The PLL will phase lock the output clock ‘CLKOUTB’ to the reference-
input clock 'CLKINB'. If the Voltage Controlled Oscillator (VCO) is set for the correct operating frequency range, and
the loop has been made stable by the correct choice of the charge pump current, then the loop will accurately
adjust the VCO to align the falling edges of the ‘CLKINB’ and ‘CLKFBKB’ inputs using the phase comparator. This
phase alignment will be subject to a small average offset and a small amount of jitter due to noise sources.
delays normally associated with buffering. The PLL will phase lock the output clock ‘CLKOUTB’ to the reference-
input clock 'CLKINB'. If the Voltage Controlled Oscillator (VCO) is set for the correct operating frequency range, and
the loop has been made stable by the correct choice of the charge pump current, then the loop will accurately
adjust the VCO to align the falling edges of the ‘CLKINB’ and ‘CLKFBKB’ inputs using the phase comparator. This
phase alignment will be subject to a small average offset and a small amount of jitter due to noise sources.
The PLL in the GP4020 has been configured for Clock Multiplication, where the output frequency is a multiplied
version of the reference input clock frequency. To achieve clock multiplication, a programmable divider is used in
the feedback path of the PLL, as shown in Figure 14.6 below. A 5-bit programmable divider has been designed
into the macro-cell. By using the clock multiplication mode of the PLL it is possible to generate a whole range of
output frequencies of integer multiples of the input clock.
version of the reference input clock frequency. To achieve clock multiplication, a programmable divider is used in
the feedback path of the PLL, as shown in Figure 14.6 below. A 5-bit programmable divider has been designed
into the macro-cell. By using the clock multiplication mode of the PLL it is possible to generate a whole range of
output frequencies of integer multiples of the input clock.
Figure 14.6 PLL Programmable Divider Configuration
Either the output from the Processor Crystal Oscillator or a divided version of M_CLK can be used as the input to a
Phase Locked Loop (PLL). The output of the PLL can then be used to generate UART_CLK and subsequently
B
Phase Locked Loop (PLL). The output of the PLL can then be used to generate UART_CLK and subsequently
B
µILD_CLK for the Firefly MF1 Core.
The PLL can be disabled by PLL_PD being high, or by PLL sleep mode. The clock out of the PLL will remain
disabled for 6 * 32kHz clock cycles (from the Real Time Clock Block) after PLL enabled (to ensure the PLL is stable
before it is used to clock 'Firefly'). The PLL output will also be disabled for 6 * 32kHz clock cycles by any reset
source, or due to PLL_IN_SEL changing.
disabled for 6 * 32kHz clock cycles (from the Real Time Clock Block) after PLL enabled (to ensure the PLL is stable
before it is used to clock 'Firefly'). The PLL output will also be disabled for 6 * 32kHz clock cycles by any reset
source, or due to PLL_IN_SEL changing.
PIN
DESCRIPTION
CLKINB
PLL input clock reference pin.
CLKFBKB
Clock feedback pin. This pin is connected to a node on the chip (usually the output of a clock buffer) via an
inverting gate that is required to be phase aligned with the input clock. All phase synchronisation is to the falling
edges of ‘CLKFBKB’ (these are the rising edges of the inverter input). The signal on ‘CLKFBKB’ is always be
derived from ‘CLKOUTB’ when the PLL is in normal operation. If the feedback link is broken then the PLL will lock
up at a high frequency.
inverting gate that is required to be phase aligned with the input clock. All phase synchronisation is to the falling
edges of ‘CLKFBKB’ (these are the rising edges of the inverter input). The signal on ‘CLKFBKB’ is always be
derived from ‘CLKOUTB’ when the PLL is in normal operation. If the feedback link is broken then the PLL will lock
up at a high frequency.
CLKOUTB
PLL clock output pin. This pin is used to drive the device’s clock buffer after inversion.