Arm Enterprises GP4020 Manuale Utente
1: Introduction
2
GP4020 GPS Baseband Processor Design Manual
1.3 Functional
Description
12 CHANNEL
GPS
CORRELATOR
RAM
(2k x 32)
MPC
UIM
ARM7TDMI
MICRO
JTAG
UART1
DMAC
TIC
SSM
INTC
Firefly
MF1 Core
SYSTEM
CLOCK
GENERATOR
UART2
BSIO
GPIO
PLL
BOOT
ROM
(512 x 16)
GPIO[7:0]
BSIO
U1RXD
U1TXD
G
P
IO
[7:0]
U2TXD
U2RXD
SIGN0
MAG0
SAMPCLK
CLK_T
CLK_I
REAL
TIME
CLOCK
U
IM
B
U
S
U
IM
B
U
S
UIM BUS
B
u
IL
D
B
U
S
B
u
IL
D
B
U
S
B
u
IL
D
B
U
S
PR_XOUT
PR_XIN
M_CLK
BuILD_CLK
T
EST
M
O
D
E
RTC_XIN
RF_PLL_LOCK
IEXTINT2
1PPS
TIMEMARK
GENERATOR
TIMEMARK / TIC
R
E
LO
A
D
_TI
C
TI
C
PERIPHERAL
CONTROL
LOGIC
NRESET
UART_CLK
BuILD_CLK
UART_CLK
UART_INT
W
A
T
CH_
IN
T
W
A
T
CH_
EN
ACCUM_INT
MEAS_INT
NRESET
TIC_INT
PER_
INT
N
S
R
ESET
DI
S
C
IO
RTC_XOUT
G
P
IO
[7:0]
W
A
T
CH_
T
M
GP4020
NRESET
SD
AT
A[
15
:0
]
SWAI
T
NS
CS
[2
:1
]
NS
CS
[0
]
S
A
D
D
[19:
0]
S
A
D
D
[19:0]
N
S
WE
[1:0]
NS
O
E
NS
UB
RAW
T
IME
MA
R
K
CK100KHz
DISCOP
JTAG INTERFACE
JT
A
G
NRESET
UART
_
C
L
K
NRESET
PLLDT1
PLLAT1
RTC_CLK
RTC_CMP_INT
M_
C
L
K
TIMEMARK
T
IME
MA
R
K
R
F
_P
LL_LO
C
K
NPOR_RESET
NPOR_
RESET
RESET
MU
LT
I_F
N
IO
TI
C
T
EST
P
O
W
E
R
_GOOD
S
IGN0
/ MA
G0
S
IGN1
/ MA
G1
POWER CONTROL LINES
IN
T
_
NCS0
TI
C
_
IN
T
DISCIO /
DISCIP1
DISCIP1
TEST
SSM
BDI
A
G
/ XPI
N I
O
TC
K
TD
I
TD
O
TM
S
NICE
NTRST
NSCS[0]
SDATA[
1
5
:0
]
M
EAS_
IN
T
ACCUM
_
INT
NRESET
DREQ2
DACK
DACK2
DREQ
WDOG
Figure 1.1 GP4020 Block Diagram
The GP4020 is a complete baseband processor for Navstar GPS C/A code signals. It incorporates a 12-channel
GPS correlator, a Zarlink Firefly MF1 micro-controller core (incorporating the ARM7TDMI Thumb microprocessor),
Real time Clock, 8k bytes of on-chip SRAM and a boot ROM. The GP4020 uses a fully configurable memory
interface, allowing the use of both 8-bit and 16-bit external memory. A Block Diagram of the GP4020 appears in
Figure 1.1 GP4020 Block Diagram" above.
GPS correlator, a Zarlink Firefly MF1 micro-controller core (incorporating the ARM7TDMI Thumb microprocessor),
Real time Clock, 8k bytes of on-chip SRAM and a boot ROM. The GP4020 uses a fully configurable memory
interface, allowing the use of both 8-bit and 16-bit external memory. A Block Diagram of the GP4020 appears in
Figure 1.1 GP4020 Block Diagram" above.