Acer imedia S3811 Manuale Utente
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Power-On Self-Test (POST)
Each time you turn on the system, the Power-on Self Test (POST) is initiated. Several items are tested
during POST, but is for the most part transparent to the user.
The Power-On Self Test (POST) is a BIOS procedure that boots the system, initializes and diagnoses the
system components, and controls the operation of the power-on password option. If POST discovers errors
in system operations at power-on, it displays error messages on screen, generates a check point
code at port 80h or even halts the system if the error is fatal.
during POST, but is for the most part transparent to the user.
The Power-On Self Test (POST) is a BIOS procedure that boots the system, initializes and diagnoses the
system components, and controls the operation of the power-on password option. If POST discovers errors
in system operations at power-on, it displays error messages on screen, generates a check point
code at port 80h or even halts the system if the error is fatal.
The main components on the main board that must be diagnosed and/or initialized by POST to ensure
system functionality are as follows:
l
Microprocessor with built-in numeric co-processor and cache memory subsystem
l
Direct Memory Access (DMA) controller
l
Interrupt system
l
Three programmable timers
l
ROM subsystem
l
RAM subsystem
l
CMOS RAM subsystem and real time clock/calendar with battery backup
l
Onboard parallel interface controller
l
Embedded hard disk interface and one diskette drive interface
l
Keyboard and auxiliary device controllers
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I/O ports
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One parallel port
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One PS/2-compatible mouse port
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One PS/2-compatible keyboard port
NOTE: When Post executes a task, it uses a series of preset numbers called check points to be latched
at port 80h, indicating the stages it is currently running. This latch can be read and shown on a debug
board.
The following table describes the BIOS common tasks carried out by POST. Each task is denoted by an
unique check point number. For other unique check point numbers that are not listed in the table, refer to
the corresponding product service guide.
at port 80h, indicating the stages it is currently running. This latch can be read and shown on a debug
board.
The following table describes the BIOS common tasks carried out by POST. Each task is denoted by an
unique check point number. For other unique check point numbers that are not listed in the table, refer to
the corresponding product service guide.
Post Checkpoints List: The list may vary accordingly depending on your BIOS
Checkpoint
Description
03
Disable NMI, Parity,video for EGA, and DMA controllers. Initialize BIOS, POST,
Runtime data area. Also initialize BIOS modules on POST entry and GPNV area.
Initialized CMOS as mentioned in the Kernel Variable "wCMOSFlags."
Runtime data area. Also initialize BIOS modules on POST entry and GPNV area.
Initialized CMOS as mentioned in the Kernel Variable "wCMOSFlags."
04
Check CMOS diagnostic byte to determine if battery power is OK and CMOS
checksum is OK. Verify CMOS checksum manually by reading storage area.
If the CMOS checksum is bad, update CMOS with power-on default values and
clear passwords. Initialize status register A.
checksum is OK. Verify CMOS checksum manually by reading storage area.
If the CMOS checksum is bad, update CMOS with power-on default values and
clear passwords. Initialize status register A.
05
Initializes the interrupt controlling hardware (generally PIC) and interrupt vector
table.
table.
06
Do R/W test to CH-2 count reg. Initialize CH-0 as system timer. Install the
POSTINT1Ch handler. Enable IRQ-0 in PIC for system timer interrupt. Traps
INT1Ch vector to "POSTINT1ChHandlerBlock."
POSTINT1Ch handler. Enable IRQ-0 in PIC for system timer interrupt. Traps
INT1Ch vector to "POSTINT1ChHandlerBlock."
07
Fixes CPU POST interface calling pointer.