Texas Instruments TMS320VC5402 Scheda Tecnica
/
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
1
POST OFFICE BOX 1443
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HOUSTON, TEXAS 77251–1443
Advanced Multibus Architecture With Three
Separate 16-Bit Data Memory Buses and
One Program Memory Bus
Separate 16-Bit Data Memory Buses and
One Program Memory Bus
40-Bit Arithmetic Logic Unit (ALU),
Including a 40-Bit Barrel Shifter and Two
Independent 40-Bit Accumulators
Including a 40-Bit Barrel Shifter and Two
Independent 40-Bit Accumulators
17-
×
17-Bit Parallel Multiplier Coupled to a
40-Bit Dedicated Adder for Non-Pipelined
Single-Cycle Multiply/Accumulate (MAC)
Operation
Single-Cycle Multiply/Accumulate (MAC)
Operation
Compare, Select, and Store Unit (CSSU) for
the Add/Compare Selection of the Viterbi
Operator
the Add/Compare Selection of the Viterbi
Operator
Exponent Encoder to Compute an
Exponent Value of a 40-Bit Accumulator
Value in a Single Cycle
Exponent Value of a 40-Bit Accumulator
Value in a Single Cycle
Two Address Generators With Eight
Auxiliary Registers and Two Auxiliary
Register Arithmetic Units (ARAUs)
Auxiliary Registers and Two Auxiliary
Register Arithmetic Units (ARAUs)
Data Bus With a Bus-Holder Feature
Extended Addressing Mode for 1M
×
16-Bit
Maximum Addressable External Program
Space
Space
4K x 16-Bit On-Chip ROM
16K x 16-Bit Dual-Access On-Chip RAM
Single-Instruction-Repeat and
Block-Repeat Operations for Program Code
Block-Repeat Operations for Program Code
Block-Memory-Move Instructions for
Efficient Program and Data Management
Efficient Program and Data Management
Instructions With a 32-Bit Long Word
Operand
Operand
Instructions With Two- or Three-Operand
Reads
Reads
Arithmetic Instructions With Parallel Store
and Parallel Load
and Parallel Load
Conditional Store Instructions
Fast Return From Interrupt
On-Chip Peripherals
– Software-Programmable Wait-State
– Software-Programmable Wait-State
Generator and Programmable Bank
Switching
Switching
– On-Chip Phase-Locked Loop (PLL) Clock
Generator With Internal Oscillator or
External Clock Source
External Clock Source
– Two Multichannel Buffered Serial Ports
(McBSPs)
– Enhanced 8-Bit Parallel Host-Port
Interface (HPI8)
– Two 16-Bit Timers
– Six-Channel Direct Memory Access
– Six-Channel Direct Memory Access
(DMA) Controller
Power Consumption Control With IDLE1,
IDLE2, and IDLE3 Instructions With
Power-Down Modes
IDLE2, and IDLE3 Instructions With
Power-Down Modes
CLKOUT Off Control to Disable CLKOUT
On-Chip Scan-Based Emulation Logic,
IEEE Std 1149.1
IEEE Std 1149.1
†
(JTAG) Boundary Scan
Logic
10-ns Single-Cycle Fixed-Point Instruction
Execution Time (100 MIPS) for 3.3-V Power
Supply (1.8-V Core)
Execution Time (100 MIPS) for 3.3-V Power
Supply (1.8-V Core)
Available in a 144-Pin Plastic Low-Profile
Quad Flatpack (LQFP) (PGE Suffix) and a
144-Pin Ball Grid Array (BGA) (GGU Suffix)
Quad Flatpack (LQFP) (PGE Suffix) and a
144-Pin Ball Grid Array (BGA) (GGU Suffix)
NOTE:This data sheet is designed to be used in conjunction with the
TMS320C5000 DSP Family Functional Overview
(literature number SPRU307).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright
2000, Texas Instruments Incorporated
† IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
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