Motorola MPC8260 Manuale Utente
6-2
MPC8260 PowerQUICC II UserÕs Manual
MOTOROLA
Part III. The Hardware Interface
Figure 6-1. MPC8260 External Signals
6.2 Signal Descriptions
The MPC8260 system bus, shown in Table 6-1, consists of all the signals that interface with
the external bus. Many of these pins perform different functions, depending on how the user
assigns them.
the external bus. Many of these pins perform different functions, depending on how the user
assigns them.
VCCSYN/GNDSYN/VCCSYN1//VD-
DH/VDD/VSS ¾¾¾>100
M
P
C
8
2
6
0
2
6
0
6
0
x
0
x
B
U
S
U
S
32
<¾¾> A[0Ð31]
PAR/
L_A14
<¾¾> 1
L
O
C
A
C
A
L
B
U
S
U
S
5
<¾¾> TT[0Ð4]
SMI/FRAME/
L_A15
<¾¾> 1
4
<¾¾> TSIZ[0Ð3]
TRDY/
L_A16
<¾¾> 1
1
<¾¾> TBST
CKSTOP_OUT/IRDY/
L_A17
<¾¾> 1
1
<¾¾> GBL/IRQ1
STOP/
L_A18
<¾¾> 1
1
<¾¾> CI/BADDR29/IRQ2
DEVSEL/
L_A19
<¾¾> 1
1
<¾¾> WT/BADDR30/IRQ3
IDSEL/
L_A20
<¾¾> 1
1
<¾¾¾ L2_HIT/IRQ4
PERR/
L_A21
<¾¾> 1
1
<¾¾> CPU_BG/BADDR31/IRQ5
1
¾¾¾> CPU_DBG
1
¾¾¾> CPU_BR
SERR/
L_A22
<¾¾> 1
1
<¾¾> BR
REQ0/
L_A23
<¾¾> 1
1
<¾¾> BG
REQ1/
L_A24
<¾¾> 1
1
<¾¾> ABB/IRQ2
GNT0/
L_A25
<¾¾> 1
1
<¾¾> TS
GNT1/
L_A26
<¾¾¾ 1
1
<¾¾> AACK
CLK/
L_A27
<¾¾> 1
1
<¾¾> ARTRY
CORE_SRESET/RST/
L_A28
<¾¾> 1
1
<¾¾> DBG
INTA/
L_A29
<¾¾> 1
1
<¾¾> DBB/IRQ3
LOCK/
L_A30
<¾¾> 1
64
<¾¾> D[0Ð63]
L_A31
<¾¾> 1
1
<¾¾> NC/DP0/RSRV/EXT_BR2
AD[0–31]/
LCL_D[0Ð31]
<¾¾> 32
1
<¾¾> IRQ1/DP1/EXT_BG2
C/BE[0–3]/
LCL_DP[0Ð3]
<¾¾> 4
1
<¾¾> IRQ2/DP2/TLBISYNC/EXT_DBG2
LBS[0Ð3]/LSDDQM[0Ð3]/LWE[0Ð3]
<¾¾¾ 4
M
E
M
C
1
<¾¾> IRQ3/DP3/CKSTP_OUT/EXT_BR3
1
<¾¾> IRQ4/DP4/CORE_SRESET/EXT_BG3
LGPL0/LSDA10
<¾¾¾ 1
1
<¾¾> IRQ5/DP5/TBEN/EXT_DBG3
LGPL1/LSDWE
<¾¾¾ 1
1
<¾¾> IRQ6/DP6/CSE0
LGPL2/LSDRAS/LOE
<¾¾¾ 1
1
<¾¾> IRQ7/DP7/CSE1
LGPL3/LSDCAS
<¾¾¾ 1
1
<¾¾> PSDVAL
LPBS/LGPL4/LUPWAIT/LGTA
<¾¾> 1
1
<¾¾> TA
LGPL5
<¾¾> 1
1
<¾¾> TEA
LWR
<¾¾> 1
1
<¾¾> IRQ0/NMI_OUT
PA[0Ð31]
<¾¾> 32
P
I
O
1
<¾¾> IRQ7/INT_OUT/APE
PB[4Ð31]
<¾¾> 28
M
E
M
C
10
¾¾¾> CS[0Ð9]
PC[0Ð31]
<¾¾> 32
1
<¾¾> CS[10]/BCTL1/DBG_DIS
PD[4Ð31]
<¾¾> 28
1
<¾¾> CS[11]/AP[0]
PORESET
¾¾¾> 1
R
S
S
T
C
L
K
2
¾¾¾> BADDR[27Ð28]
RSTCONF
¾¾¾> 1
1
¾¾¾> ALE
HRESET
<¾¾> 1
1
¾¾¾> BCTL0
SRESET
<¾¾> 1
8
¾¾¾> PWE[0Ð7]/PSDDQM[0Ð7]/PBS[0Ð7]
QREQ
<¾¾¾ 1
1
¾¾¾> PSDA10/PGPL0
1
¾¾¾> PSDWE/PGPL1
XFC
¾¾¾> 1
1
¾¾¾> POE/PSDRAS/PGPL2
1
¾¾¾> PSDCAS/PGPL3
CLKIN
¾¾¾> 1
1
<¾¾> PGTA/PUPMWAIT/PGPL4/PPBS
TRIS
¾¾¾> 1
1
¾¾¾> PSDAMUX/PGPL5
BNKSEL[0]/TC[0]/AP[1]/MODCK1
<¾¾> 1
J
T
T
A
G
G
1
<¾¾- TMS
BNKSEL[1]/TC[1]/AP[2]/MODCK2
<¾¾> 1
1
<¾¾¾TDI
BNKSEL[2]/TC[2]/AP[3]/MODCK3
<¾¾> 1
1
<¾¾- TCK
TERM[0Ð1]
¾¾¾> 2
1
<¾¾- TRST
NC
¾¾¾> 4
1
-¾¾> TDO