Motorola DSP56012 Manuale Utente

The read-only status bit Host Busy (HBUSY) indicates that the I

2

C bus is busy (when 

in the I

2

C mode) or that the SHI itself is busy (when in the SPI mode). When 

operating in the I

2

C mode, HBUSY is set after the SHI detects a Start event and 

remains set until a Stop event is detected. When operating in the Slave SPI mode, 
HBUSY is set while SS is asserted. When operating in the Master SPI mode, HBUSY is 
set if the HTX register is not empty or if the IOSR is not empty. HBUSY is cleared 
otherwise. HBUSY is cleared by hardware reset, software reset, SHI individual reset, 
and during the Stop state.

The SPI bus consists of two serial data lines (MISO and MOSI), a clock line (SCK), 
and a Slave Select line (SS).During an SPI transfer, a byte is shifted out one data pin 
while a different byte is simultaneously shifted in through a second data pin. It can 
be viewed as two 8-bit shift registers connected together in a circular manner, where 
one shift register is located on the master side and the other on the slave side. Thus 
the data bytes in the master device and slave device are effectively exchanged. The 
MISO and MOSI data pins are used for transmitting and receiving serial data. When 
the SPI is configured as a master, MISO is the master data input line, and MOSI is the 
master data output line. When the SPI is configured as a slave device, these pins 
reverse roles. 

Clock control logic allows a selection of clock polarity and a choice of two 
fundamentally different clocking protocols to accommodate most available 
synchronous serial peripheral devices. When the SPI is configured as a master, the 
control bits in the HCKR select the appropriate clock rate, as well as the desired clock 
polarity and phase format (see 

The SS line allows individual selection of a slave SPI device; slave devices that are not 
selected do not interfere with SPI bus activity (i.e., they keep their MISO output pin 
in the high-impedance state). When the SHI is configured as an SPI master device, 
the SS line should be held high. If the SS line is driven low when the SHI is in SPI 
Master mode, a bus error will be generated (the HCSR HBER bit will be set).