Motorola DSP56012 Manuale Utente
Serial Audio Interface
Serial Audio Interface Programming Model
MOTOROLA
DSP56012 User’s Manual
6-17
6.3.3
SAI Receive Data Registers (RX0 and RX1)
The Receive data registers (RX0 and RX1) are 24-bit read-only registers that accept
data from the receive shift registers when all bits of the incoming data words have
been received. The receive data registers alternately contain left-channel and
right-channel data. The first data to appear in the data registers, after enabling
operation of the respective receivers, will be the data for the left channel.
data from the receive shift registers when all bits of the incoming data words have
been received. The receive data registers alternately contain left-channel and
right-channel data. The first data to appear in the data registers, after enabling
operation of the respective receivers, will be the data for the left channel.
6.3.4
Transmitter Control/Status Register (TCS)
The TCS is a 16-bit read/write control/status register used to direct the operation of
the transmit section in the SAI. The TCS register is shown in Figure 6-4 on page 6-8.
The control bits in the TCS determine the serial format of the data transfers. The
status bits of the TCS are used by the DSP programmer to interrogate the status of the
transmitter section. Separate transmit enable and interrupt enable bits are also
provided in the TCS. When read by the DSP, the TCS appears on the two low-order
bytes of the 24-bit word, and the high-order byte is read as 0s. Hardware reset and
software reset clear all the bits in TCS. When the T0EN, T1EN, and T2EN bits are
cleared, the SAI transmitter section is disabled and it enters the individual reset state
after a one instruction cycle delay. While in the Stop or individual reset state, the
status bits in TCS are cleared. Stop or individual reset do not affect the TCS control
bits. The programmer should change TCS control bits (except for TXIE) only while
the transmitter section is in the individual reset state, otherwise improper operation
may result. The TCS bits are described in the following paragraphs.
the transmit section in the SAI. The TCS register is shown in Figure 6-4 on page 6-8.
The control bits in the TCS determine the serial format of the data transfers. The
status bits of the TCS are used by the DSP programmer to interrogate the status of the
transmitter section. Separate transmit enable and interrupt enable bits are also
provided in the TCS. When read by the DSP, the TCS appears on the two low-order
bytes of the 24-bit word, and the high-order byte is read as 0s. Hardware reset and
software reset clear all the bits in TCS. When the T0EN, T1EN, and T2EN bits are
cleared, the SAI transmitter section is disabled and it enters the individual reset state
after a one instruction cycle delay. While in the Stop or individual reset state, the
status bits in TCS are cleared. Stop or individual reset do not affect the TCS control
bits. The programmer should change TCS control bits (except for TXIE) only while
the transmitter section is in the individual reset state, otherwise improper operation
may result. The TCS bits are described in the following paragraphs.
6.3.4.1
TCS Transmitter 0 Enable (T0EN)—Bit 0
The read/write control bit T0EN enables the operation of the SAI Transmitter 0.
When T0EN is set, Transmitter 0 is enabled. When T0EN is cleared, Transmitter 0 is
disabled and the SDO0 line is set to high level. If T0EN, T1EN, and T2EN are cleared,
the SAI transmitter section is disabled and enters the individual reset state. The T0EN
bit is cleared during hardware reset and software reset.
When T0EN is set, Transmitter 0 is enabled. When T0EN is cleared, Transmitter 0 is
disabled and the SDO0 line is set to high level. If T0EN, T1EN, and T2EN are cleared,
the SAI transmitter section is disabled and enters the individual reset state. The T0EN
bit is cleared during hardware reset and software reset.
6.3.4.2
TCS Transmitter 1 Enable (T1EN)—Bit 1
The read/write control bit T1EN enables the operation of the SAI Transmitter 1.
When T1EN is set, Transmitter 1 is enabled. When T1EN is cleared, Transmitter 1 is
disabled and the SDO1 line is set to high level. If T0EN, T1EN and T2EN are cleared,
the SAI transmitter section is disabled and enters the individual reset state. The T1EN
bit is cleared during hardware reset and software reset.
When T1EN is set, Transmitter 1 is enabled. When T1EN is cleared, Transmitter 1 is
disabled and the SDO1 line is set to high level. If T0EN, T1EN and T2EN are cleared,
the SAI transmitter section is disabled and enters the individual reset state. The T1EN
bit is cleared during hardware reset and software reset.