Intel Core™ i5-750 Processor (8M Cache, 2.66 GHz) BX8060515750 Manuale Utente
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BX8060515750
Datasheet, Volume 2
239
Processor Uncore Configuration Registers
4.10.3
MC_CHANNEL_0_DIMM_INIT_PARAMS
MC_CHANNEL_1_DIMM_INIT_PARAMS
Initialization sequence parameters are stored in this register. Each field is 2^n count.
Device:
4, 5
Function: 0
Offset:
58h
Access as a DWord
Bit
Attr
Default
Description
31:27
RO
0
Reserved
26
RV
0
Reserved
25
RV
0
Reserved
24
RV
0
Reserved
23
RV
0
Reserved
22
RV
0
Reserved
21:17
RW
15
WRDQDQS_DELAY
Specifies the delay in DCLKs between reads and writes for WRDQDQS
Specifies the delay in DCLKs between reads and writes for WRDQDQS
training.
16
RW
0
WRLEVEL_DELAY
Specifies the delay used between write CAS indications for write leveling
Specifies the delay used between write CAS indications for write leveling
training.
0 = 16 DCLKs
0 = 16 DCLKs
1 = 32 DCLKs
15
RV
0
Reserved
14:10
RW
0
PHY_FSM_DELAY
Global timer used for bounding the physical layer training. If the timer
Global timer used for bounding the physical layer training. If the timer
expires, the FSM will go to the next step and the counter will be reloaded
with PHY_FSM_DELAY value. Units are 2^n dclk.
9:5
RW
0
BLOCK_CKE_DELAY
Delay in ns from when clocks and command are valid to the point CKE is
Delay in ns from when clocks and command are valid to the point CKE is
allowed to be asserted. Units are in 2^n uclk.
4:0
RW
0
RESET_ON_TIME
Reset will be asserted for the time specified. Units are 2^n Uclk.
Reset will be asserted for the time specified. Units are 2^n Uclk.