Motorola IH5 Manuale Utente
5-2
Computer Group Literature Center Web Site
Remote Start Via the PCI Bus
5
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A command data and result field. This field provides the data, if any,
needed by the command and provides the response from PPCBug
upon command completion. The meaning of the bits in this field are
specific to each command opcode.
needed by the command and provides the response from PPCBug
upon command completion. The meaning of the bits in this field are
specific to each command opcode.
Additionally, certain commands require more information than can be
contained within the data and result fields of the scratch pad register. To
provide this information, the interface provides four ‘virtual’ registers. The
contents of these registers are used in certain commands. The contents of
the registers can be accessed via commands issued through the scratch
register. These registers are designated by the monikers VR0, VR1, VR2
and VR3.
contained within the data and result fields of the scratch pad register. To
provide this information, the interface provides four ‘virtual’ registers. The
contents of these registers are used in certain commands. The contents of
the registers can be accessed via commands issued through the scratch
register. These registers are designated by the monikers VR0, VR1, VR2
and VR3.
During reset startup, the command/response register is written with a
specific reset pattern. This indicates that the local CPU has been reset and
is ready to accept commands through the command/response register.
specific reset pattern. This indicates that the local CPU has been reset and
is ready to accept commands through the command/response register.
PPCBug uses certain areas of memory and I/O devices for it’s own
operation. This interface allows the host CPU to write and read any
location on the local CPU bus including those in use by the firmware. Host
CPUs should interrogate the firmware via the memory size query
command (described in the following paragraph) and avoid overwriting
memory which is in-use by firmware - otherwise, erratic behavior may
result.
operation. This interface allows the host CPU to write and read any
location on the local CPU bus including those in use by the firmware. Host
CPUs should interrogate the firmware via the memory size query
command (described in the following paragraph) and avoid overwriting
memory which is in-use by firmware - otherwise, erratic behavior may
result.