Fujitsu mb91192 Manuale Utente
143
6.2
Capstan Input
The capstan input section is comprised of a multiplying circuit, 8-bit programmable
divider, and mask timer. This section explains the operation of each section and control
register.
divider, and mask timer. This section explains the operation of each section and control
register.
■
Block Diagram of Capstan Input
Figure 6.2-1 Block Diagram of Capstan Input
■
Register List of Capstan Input
Figure 6.2-2 Register list of Capstan Input
S
R
Load (Sync)
Load (Sync)
Write ST
Internal Bus
2 multipli-
cation
cation
CFGD
FCLR
CMTS
MTCS
DUB
CAPC
CAPMTC
00
00
QS
R1
R2
R2
8bit
CAPDVC
2
14
/fch
2
10
/fch
CFG
Programmable devider
(from FRC
FRC9, 13)
FRC9, 13)
START (Mask Enable)
Mask Timer
Mask End
DVCFG Free
(Mask Disable)
RS-FF
DVCFG
(to FRC)
(to FRC)
M
P
X
X
M
P
X
X
Capstan input control register
Capstan timer control register
Capstan control register
7
0
bit
Address:
000050
H
000051
H
000052
H
CAPDVC
CAPMTC
CAPC