Fujitsu mb91192 Manuale Utente
213
12.2
Register of 8-bit Pulse Width Counter
The register configuration/functions of the 8-bit pulse width counter are mentioned.
■
PWC Control Register (PWCC)
Figure 12.2-1 PWC Control Register (PWCC)
[bit7]:Test
It is test bit.
[bit6 to 4]:
It is an unused bit.
[bit3]:CAPE
It is capture enable bit.
The read value of this bit is always "0".
[bit2]:CAPF
It is capture flag.
[bit1]:MSKE
It is mask (PMSK) input enable bit.
7 6 5 4 3 2 1 0
0--- 0X00
B
Initial value
bit
Address: 000094
H
Test
CAPE
CAPF
MSKE
ST
W
R
R/W
R/W
R/W
Access
Please set "0".
0 None
1
Clear CAPF bit and become capture enable status.
0
No capture data. Capture enable status
1
Capture data. Capture disable status
0
PMSK input interdiction
1
PMSK input permission