Samsung P8245 Manuale Utente
I/O PORTS
S3C8245/P8245/C8249/P8249
9-4
Port 0 Control Register, High Byte (P0CONH)
E0H, Set 1, Bank 0, R/W
.7
.6
.5
.4
.3
.2
.1
.0
MSB
LSB
P0.7
(INT7)
P0.6
(INT6)
P0.5
(INT5)
P0.4
(INT4)
P0CONH bit-pair pin configuration:
00
01
10
11
Schmitt trigger input mode, pull-up, interrupt on falling edge
Schmitt trigger input mode, interrupt on rising edge
Schmitt trigger input mode, interrupt on rising or falling edge
Output mode, push-pull
Figure 9-1. Port 0 High-Byte Control Register (P0CONH)
Port 0 Control Register, Low Byte (P0CONL)
E1H, Set 1, Bank 0, R/W
.7
.6
.5
.4
.3
.2
.1
.0
MSB
LSB
P0.3
(INT3)
P0.2
(INT2)
P0.1
(INT1)
P0.0
(INT0)
P0CONL bit-pair pin configuration:
00
01
10
11
Schmitt trigger input mode, pull-up, interrupt on falling edge
Schmitt trigger input mode, interrupt on rising edge
Schmitt trigger input mode, interrupt on rising or falling edge
Output mode, push-pull
Figure 9-2. Port 0 Low-Byte Control Register (P0CONL)