Manuali utente per Arm Enterprises IM-AD1

Sommario

• Contents

  5
• Preface

  7
  • About this book

    8
    • Intended audience

      8
    • Using this book

      8
    • Further reading

      9
  • Feedback

    11
    • Feedback on this document

      11
    • Feedback on the Integrator/IM-AD1

      11
• Introduction

  13
  • 1.1 About the Integrator/IM-AD1

    14
  • 1.2 Interface module features and architecture

    16
    • 1.2.1 Features

      16
    • 1.2.2 Architecture

      17
  • 1.3 Links and LEDs

    18
  • 1.4 Care of modules

    19
• Getting Started

  21
  • 2.1 Fitting the interface module

    22
  • 2.2 Setting up the logic module

    23
  • 2.3 Running the test software

    24
• Hardware Reference

  25
  • 3.1 Differences in signal routing between supported logic modules

    26
  • 3.2 UART interface

    27
  • 3.3 SPI

    29
  • 3.4 PWM interface

    30
  • 3.5 Stepper motor interface

    32
    • 3.5.1 Functional description

      32
    • 3.5.2 Stepper motor interface signal summary

      33
    • 3.5.3 Stepper motor connectors

      34
  • 3.6 GPIO

    36
  • 3.7 CAN interface

    38
  • 3.8 ADC and DAC interfaces

    42
• Reference Design Example

  47
  • 4.1 About the design example

    48
    • 4.1.1 About PrimeCells

      48
    • 4.1.2 Example architecture

      48
    • 4.1.3 Example memory map

      50
    • 4.1.4 Address assignment of logic modules

      51
    • 4.1.5 Integrator/IM-AD1 memory map

      52
  • 4.2 Example APB register peripheral

    54
    • 4.2.1 Oscillator divisor registers

      55
    • 4.2.2 Oscillator lock register

      57
    • 4.2.3 User LEDs control register

      57
    • 4.2.4 Push button interrupt register

      57
    • 4.2.5 Switches register

      58
  • 4.3 UART

    59
  • 4.4 SPI chip select register

    60
  • 4.5 Synchronous serial port

    61
  • 4.6 PWM controller

    62
  • 4.7 Stepper motor peripheral

    63
    • 4.7.1 Stepper x control register

      64
    • 4.7.2 Stepx count register

      66
    • 4.7.3 Stepx speed register

      66
  • 4.8 GPIO

    67
    • 4.8.1 Data output set register

      67
    • 4.8.2 Read data input register

      67
    • 4.8.3 Data register output clear

      67
    • 4.8.4 Read data output pins

      67
    • 4.8.5 Data direction

      68
  • 4.9 SSRAM interface

    69
  • 4.10 Vectored interrupt controller

    70
    • 4.10.1 Interrupt sources

      70
  • 4.11 CAN controller interface

    72
    • 4.11.1 CANxBase

      72
    • 4.11.2 CAN reset control register

      72
  • 4.12 ADC and DAC interface

    73
  • 4.13 Peripheral information block

    74
• Signal Descriptions

  75
  • A.1 EXPA

    76
  • A.2 EXPB

    78
  • A.3 EXPIM

    80
  • A.4 Logic analyzer connector

    82
  • A.5 Multi-ICE (JTAG)

    84
• Mechanical Specification

  85
  • B.1 Mechanical information

    86
  • B.2 Connector reference

    88
• Glossary

  89
• Index

  91
  • A

    91
  • B

    91
  • C

    91
  • D

    91
  • E

    91
  • F

    91
  • G

    92
  • I

    92
  • L

    92
  • M

    92
  • N

    92
  • O

    92
  • P

    92
  • R

    92
  • S

    92
  • U

    92
  • V

    92