Scheda Tecnica (MEGA328P-XMINI)SommarioIntroduction1Table of Contents21. Getting Started31.1. Features31.2. Design Documentation and Related Links31.3. Board Assembly31.3.1. In Customer Development Assembly31.3.2. Connecting an Arduino Shield31.3.3. Standalone Node31.4. Connecting the Kit31.4.1. Connect the Kit to Atmel Studio31.4.2. Connect the Target UART to the mEBDG COM Port31.5. Programming and Debugging41.5.1. Programming the Target Using mEDBG41.5.2. Debugging the Target Using mEDBG41.5.3. Programming the Target Using an External Programmer51.5.4. Programming the ATmega32U4 Using an External Programmer51.5.5. Programming the ATmega32U4 Using a Bootloader61.5.6. How to Install the "Bootloader PC tool"61.6. Available Example Code72. Hardware User Guide82.1. Board Overview82.2. Clock Distribution82.3. Headers and Connectors82.3.1. JTAG (J100)82.3.2. USB (J101)92.3.3. USART (J104)92.3.4. Target Digital I/O (J200 and J201)92.3.5. Target Analogue I/O (J203)102.3.6. Power (J202, J300, J301)102.3.6.1. Power supply configuration102.3.7. Target SPI (J204)112.3.8. Additional Target Signals112.3.9. Extension headers122.4. Board GUI132.4.1. LEDs132.4.2. Button132.5. Factory Programmed Data142.6. Errata143. Document Revision History15Dimensioni: 1,61 MBPagine: 16Language: EnglishApri il manuale
Scheda Tecnica (MEGA328P-XMINI)SommarioFeatures11. Pin Configurations31.1 Pin Descriptions41.1.1 VCC41.1.2 GND41.1.3 Port B (PB7:0) XTAL1/XTAL2/TOSC1/TOSC241.1.4 Port C (PC5:0)41.1.5 PC6/RESET41.1.6 Port D (PD7:0)41.1.7 AVCC51.1.8 AREF51.1.9 ADC7:6 (TQFP and QFN/MLF Package Only)52. Overview62.1 Block Diagram62.2 Comparison Between Processors73. Resources84. Data Retention85. About Code Examples86. Capacitive Touch Sensing87. AVR CPU Core97.1 Overview97.2 ALU – Arithmetic Logic Unit107.3 Status Register107.3.1 SREG – AVR Status Register117.4 General Purpose Register File117.4.1 The X-register, Y-register, and Z-register127.5 Stack Pointer137.5.1 SPH and SPL – Stack Pointer High and Stack Pointer Low Register137.6 Instruction Execution Timing147.7 Reset and Interrupt Handling147.7.1 Interrupt Response Time168. AVR Memories178.1 Overview178.2 In-System Reprogrammable Flash Program Memory178.3 SRAM Data Memory198.3.1 Data Memory Access Times208.4 EEPROM Data Memory208.4.1 EEPROM Read/Write Access208.4.2 Preventing EEPROM Corruption218.5 I/O Memory218.5.1 General Purpose I/O Registers218.6 Register Description228.6.1 EEARH and EEARL – The EEPROM Address Register228.6.2 EEDR – The EEPROM Data Register228.6.3 EECR – The EEPROM Control Register228.6.4 GPIOR2 – General Purpose I/O Register 2268.6.5 GPIOR1 – General Purpose I/O Register 1268.6.6 GPIOR0 – General Purpose I/O Register 0269. System Clock and Clock Options279.1 Clock Systems and their Distribution279.1.1 CPU Clock – clkCPU279.1.2 I/O Clock – clkI/O279.1.3 Flash Clock – clkFLASH289.1.4 Asynchronous Timer Clock – clkASY289.1.5 ADC Clock – clkADC289.2 Clock Sources289.2.1 Default Clock Source289.2.2 Clock Startup Sequence289.3 Low Power Crystal Oscillator299.4 Full Swing Crystal Oscillator309.5 Low Frequency Crystal Oscillator339.6 Calibrated Internal RC Oscillator349.7 128kHz Internal Oscillator359.8 External Clock359.9 Clock Output Buffer369.10 Timer/Counter Oscillator369.11 System Clock Prescaler369.12 Register Description389.12.1 OSCCAL – Oscillator Calibration Register389.12.2 CLKPR – Clock Prescale Register3810. Power Management and Sleep Modes4010.1 Sleep Modes4010.2 BOD Disable(1)4110.3 Idle Mode4110.4 ADC Noise Reduction Mode4110.5 Power-down Mode4110.6 Power-save Mode4210.7 Standby Mode4210.8 Extended Standby Mode4310.9 Power Reduction Register4310.10 Minimizing Power Consumption4310.10.1 Analog to Digital Converter4310.10.2 Analog Comparator4310.10.3 Brown-out Detector4310.10.4 Internal Voltage Reference4410.10.5 Watchdog Timer4410.10.6 Port Pins4410.10.7 On-chip Debug System4410.11 Register Description4510.11.1 SMCR – Sleep Mode Control Register4510.11.2 MCUCR – MCU Control Register4610.11.3 PRR – Power Reduction Register4611. System Control and Reset4811.1 Resetting the AVR4811.2 Reset Sources4811.3 Power-on Reset4911.4 External Reset5011.5 Brown-out Detection5011.6 Watchdog System Reset5111.7 Internal Voltage Reference5111.7.1 Voltage Reference Enable Signals and Start-up Time5111.8 Watchdog Timer5211.8.1 Features5211.8.2 Overview5211.9 Register Description5511.9.1 MCUSR – MCU Status Register5511.9.2 WDTCSR – Watchdog Timer Control Register5512. Interrupts5812.1 Interrupt Vectors in ATmega48A and ATmega48PA5812.2 Interrupt Vectors in ATmega88A and ATmega88PA6012.3 Interrupt Vectors in ATmega168A and ATmega168PA6312.4 Interrupt Vectors in ATmega328 and ATmega328P6612.5 Register Description6912.5.1 Moving Interrupts Between Application and Boot Space, ATmega88A/88PA, ATmega168A/168PA and ATmega328/328P6913. External Interrupts7113.1 Pin Change Interrupt Timing7113.2 Register Description7213.2.1 EICRA – External Interrupt Control Register A7213.2.2 EIMSK – External Interrupt Mask Register7313.2.3 EIFR – External Interrupt Flag Register7313.2.4 PCICR – Pin Change Interrupt Control Register7413.2.5 PCIFR – Pin Change Interrupt Flag Register7413.2.6 PCMSK2 – Pin Change Mask Register 27513.2.7 PCMSK1 – Pin Change Mask Register 17513.2.8 PCMSK0 – Pin Change Mask Register 07514. I/O-Ports7614.1 Overview7614.2 Ports as General Digital I/O7714.2.1 Configuring the Pin7714.2.2 Toggling the Pin7714.2.3 Switching Between Input and Output7814.2.4 Reading the Pin Value7814.2.5 Digital Input Enable and Sleep Modes8014.2.6 Unconnected Pins8014.3 Alternate Port Functions8114.3.1 Alternate Functions of Port B8314.3.2 Alternate Functions of Port C8614.3.3 Alternate Functions of Port D8914.4 Register Description9214.4.1 MCUCR – MCU Control Register9214.4.2 PORTB – The Port B Data Register9214.4.3 DDRB – The Port B Data Direction Register9214.4.4 PINB – The Port B Input Pins Address(1)9214.4.5 PORTC – The Port C Data Register9214.4.6 DDRC – The Port C Data Direction Register9214.4.7 PINC – The Port C Input Pins Address(1)9314.4.8 PORTD – The Port D Data Register9314.4.9 DDRD – The Port D Data Direction Register9314.4.10 PIND – The Port D Input Pins Address(1)9315. 8-bit Timer/Counter0 with PWM9415.1 Features9415.2 Overview9415.2.1 Definitions9515.2.2 Registers9515.3 Timer/Counter Clock Sources9515.4 Counter Unit9515.5 Output Compare Unit9615.5.1 Force Output Compare9715.5.2 Compare Match Blocking by TCNT0 Write9715.5.3 Using the Output Compare Unit9715.6 Compare Match Output Unit9815.6.1 Compare Output Mode and Waveform Generation9815.7 Modes of Operation9915.7.1 Normal Mode9915.7.2 Clear Timer on Compare Match (CTC) Mode9915.7.3 Fast PWM Mode10015.7.4 Phase Correct PWM Mode10115.8 Timer/Counter Timing Diagrams10315.9 Register Description10515.9.1 TCCR0A – Timer/Counter Control Register A10515.9.2 TCCR0B – Timer/Counter Control Register B10815.9.3 TCNT0 – Timer/Counter Register10915.9.4 OCR0A – Output Compare Register A10915.9.5 OCR0B – Output Compare Register B10915.9.6 TIMSK0 – Timer/Counter Interrupt Mask Register11015.9.7 TIFR0 – Timer/Counter 0 Interrupt Flag Register11016. 16-bit Timer/Counter1 with PWM11216.1 Features11216.2 Overview11216.2.1 Registers11316.2.2 Definitions11416.3 Accessing 16-bit Registers11416.3.1 Reusing the Temporary High Byte Register11716.4 Timer/Counter Clock Sources11716.5 Counter Unit11716.6 Input Capture Unit11816.6.1 Input Capture Trigger Source11916.6.2 Noise Canceler12016.6.3 Using the Input Capture Unit12016.7 Output Compare Units12016.7.1 Force Output Compare12116.7.2 Compare Match Blocking by TCNT1 Write12116.7.3 Using the Output Compare Unit12216.8 Compare Match Output Unit12216.8.1 Compare Output Mode and Waveform Generation12316.9 Modes of Operation12316.9.1 Normal Mode12316.9.2 Clear Timer on Compare Match (CTC) Mode12316.9.3 Fast PWM Mode12416.9.4 Phase Correct PWM Mode12616.9.5 Phase and Frequency Correct PWM Mode12816.10 Timer/Counter Timing Diagrams13016.11 Register Description13216.11.1 TCCR1A – Timer/Counter1 Control Register A13216.11.2 TCCR1B – Timer/Counter1 Control Register B13416.11.3 TCCR1C – Timer/Counter1 Control Register C13516.11.4 TCNT1H and TCNT1L – Timer/Counter113516.11.5 OCR1AH and OCR1AL – Output Compare Register 1 A13616.11.6 OCR1BH and OCR1BL – Output Compare Register 1 B13616.11.7 ICR1H and ICR1L – Input Capture Register 113616.11.8 TIMSK1 – Timer/Counter1 Interrupt Mask Register13616.11.9 TIFR1 – Timer/Counter1 Interrupt Flag Register13717. Timer/Counter0 and Timer/Counter1 Prescalers13917.1 Internal Clock Source13917.2 Prescaler Reset13917.3 External Clock Source13917.4 Register Description14117.4.1 GTCCR – General Timer/Counter Control Register14118. 8-bit Timer/Counter2 with PWM and Asynchronous Operation14218.1 Features14218.2 Overview14218.2.1 Registers14218.2.2 Definitions14318.3 Timer/Counter Clock Sources14318.4 Counter Unit14318.5 Output Compare Unit14418.5.1 Force Output Compare14518.5.2 Compare Match Blocking by TCNT2 Write14518.5.3 Using the Output Compare Unit14518.6 Compare Match Output Unit14618.6.1 Compare Output Mode and Waveform Generation14618.7 Modes of Operation14718.7.1 Normal Mode14718.7.2 Clear Timer on Compare Match (CTC) Mode14718.7.3 Fast PWM Mode14818.7.4 Phase Correct PWM Mode14918.8 Timer/Counter Timing Diagrams15118.9 Asynchronous Operation of Timer/Counter215218.10 Timer/Counter Prescaler15318.11 Register Description15418.11.1 TCCR2A – Timer/Counter Control Register A15418.11.2 TCCR2B – Timer/Counter Control Register B15718.11.3 TCNT2 – Timer/Counter Register15818.11.4 OCR2A – Output Compare Register A15818.11.5 OCR2B – Output Compare Register B15818.11.6 TIMSK2 – Timer/Counter2 Interrupt Mask Register15818.11.7 TIFR2 – Timer/Counter2 Interrupt Flag Register15918.11.8 ASSR – Asynchronous Status Register15918.11.9 GTCCR – General Timer/Counter Control Register16019. SPI – Serial Peripheral Interface16119.1 Features16119.2 Overview16119.3 SS Pin Functionality16619.3.1 Slave Mode16619.3.2 Master Mode16619.4 Data Modes16619.5 Register Description16819.5.1 SPCR – SPI Control Register16819.5.2 SPSR – SPI Status Register16919.5.3 SPDR – SPI Data Register17020. USART017120.1 Features17120.2 Overview17120.3 Clock Generation17220.3.1 Internal Clock Generation – The Baud Rate Generator17320.3.2 Double Speed Operation (U2Xn)17420.3.3 External Clock17420.3.4 Synchronous Clock Operation17520.4 Frame Formats17520.4.1 Parity Bit Calculation17620.5 USART Initialization17620.6 Data Transmission – The USART Transmitter17720.6.1 Sending Frames with 5 to 8 Data Bit17820.6.2 Sending Frames with 9 Data Bit17820.6.3 Transmitter Flags and Interrupts17920.6.4 Parity Generator18020.6.5 Disabling the Transmitter18020.7 Data Reception – The USART Receiver18020.7.1 Receiving Frames with 5 to 8 Data Bits18020.7.2 Receiving Frames with 9 Data Bits18120.7.3 Receive Compete Flag and Interrupt18220.7.4 Receiver Error Flags18320.7.5 Parity Checker18320.7.6 Disabling the Receiver18320.7.7 Flushing the Receive Buffer18420.8 Asynchronous Data Reception18420.8.1 Asynchronous Clock Recovery18420.8.2 Asynchronous Data Recovery18520.8.3 Asynchronous Operational Range18620.9 Multi-processor Communication Mode18720.9.1 Using MPCMn18720.10 Examples of Baud Rate Setting18820.11 Register Description19220.11.1 UDRn – USART I/O Data Register n19220.11.2 UCSRnA – USART Control and Status Register n A19220.11.3 UCSRnB – USART Control and Status Register n B19320.11.4 UCSRnC – USART Control and Status Register n C19420.11.5 UBRRnL and UBRRnH – USART Baud Rate Registers19621. USART in SPI Mode19721.1 Features19721.2 Overview19721.3 Clock Generation19721.4 SPI Data Modes and Timing19821.5 Frame Formats19821.5.1 USART MSPIM Initialization19921.6 Data Transfer20121.6.1 Transmitter and Receiver Flags and Interrupts20221.6.2 Disabling the Transmitter or Receiver20221.7 AVR USART MSPIM vs. AVR SPI20321.8 Register Description20421.8.1 UDRn – USART MSPIM I/O Data Register20421.8.2 UCSRnA – USART MSPIM Control and Status Register n A20421.8.3 UCSRnB – USART MSPIM Control and Status Register n B20421.8.4 UCSRnC – USART MSPIM Control and Status Register n C20521.8.5 USART MSPIM Baud Rate Registers – UBRRnL and UBRRnH20622. 2-wire Serial Interface20722.1 Features20722.2 2-wire Serial Interface Bus Definition20722.2.1 TWI Terminology20822.2.2 Electrical Interconnection20822.3 Data Transfer and Frame Format20822.3.1 Transferring Bits20822.3.2 START and STOP Conditions20922.3.3 Address Packet Format20922.3.4 Data Packet Format21022.3.5 Combining Address and Data Packets into a Transmission21022.4 Multi-master Bus Systems, Arbitration and Synchronization21122.5 Overview of the TWI Module21322.5.1 SCL and SDA Pins21322.5.2 Bit Rate Generator Unit21322.5.3 Bus Interface Unit21422.5.4 Address Match Unit21422.5.5 Control Unit21422.6 Using the TWI21522.7 Transmission Modes21722.7.1 Master Transmitter Mode21822.7.2 Master Receiver Mode22122.7.3 Slave Receiver Mode22322.7.4 Slave Transmitter Mode22622.7.5 Miscellaneous States22922.7.6 Combining Several TWI Modes22922.8 Multi-master Systems and Arbitration23022.9 Register Description23122.9.1 TWBR – TWI Bit Rate Register23122.9.2 TWCR – TWI Control Register23122.9.3 TWSR – TWI Status Register23222.9.4 TWDR – TWI Data Register23322.9.5 TWAR – TWI (Slave) Address Register23322.9.6 TWAMR – TWI (Slave) Address Mask Register23423. Analog Comparator23523.1 Overview23523.2 Analog Comparator Multiplexed Input23523.3 Register Description23623.3.1 ADCSRB – ADC Control and Status Register B23623.3.2 ACSR – Analog Comparator Control and Status Register23623.3.3 DIDR1 – Digital Input Disable Register 123724. Analog-to-Digital Converter23824.1 Features23824.2 Overview23824.3 Starting a Conversion24024.4 Prescaling and Conversion Timing24124.5 Changing Channel or Reference Selection24324.5.1 ADC Input Channels24424.5.2 ADC Voltage Reference24424.6 ADC Noise Canceler24424.6.1 Analog Input Circuitry24424.6.2 Analog Noise Canceling Techniques24524.6.3 ADC Accuracy Definitions24624.7 ADC Conversion Result24824.8 Temperature Measurement24824.9 Register Description24924.9.1 ADMUX – ADC Multiplexer Selection Register24924.9.2 ADCSRA – ADC Control and Status Register A25024.9.3 ADCL and ADCH – The ADC Data Register25124.9.4 ADCSRB – ADC Control and Status Register B25224.9.5 DIDR0 – Digital Input Disable Register 025225. debugWIRE On-chip Debug System25425.1 Features25425.2 Overview25425.3 Physical Interface25425.4 Software Break Points25525.5 Limitations of debugWIRE25525.6 Register Description25525.6.1 DWDR – debugWire Data Register25526. Self-Programming the Flash, ATmega 48A/48PA25626.1 Overview25626.1.1 Performing Page Erase by SPM25626.1.2 Filling the Temporary Buffer (Page Loading)25626.1.3 Performing a Page Write25726.2 Addressing the Flash During Self-Programming25726.2.1 EEPROM Write Prevents Writing to SPMCSR25726.2.2 Reading the Fuse and Lock Bits from Software25826.2.3 Preventing Flash Corruption25926.2.4 Programming Time for Flash when Using SPM25926.2.5 Simple Assembly Code Example for a Boot Loader26026.3 Register Description26226.3.1 SPMCSR – Store Program Memory Control and Status Register26227. Boot Loader Support – Read-While-Write Self-Programming26427.1 Features26427.2 Overview26427.3 Application and Boot Loader Flash Sections26427.3.1 Application Section26427.3.2 BLS – Boot Loader Section26427.4 Read-While-Write and No Read-While-Write Flash Sections26527.4.1 RWW – Read-While-Write Section26527.4.2 NRWW – No Read-While-Write Section26527.5 Boot Loader Lock Bits26727.6 Entering the Boot Loader Program26827.7 Addressing the Flash During Self-Programming26927.8 Self-Programming the Flash27027.8.1 Performing Page Erase by SPM27027.8.2 Filling the Temporary Buffer (Page Loading)27027.8.3 Performing a Page Write27027.8.4 Using the SPM Interrupt27127.8.5 Consideration While Updating BLS27127.8.6 Prevent Reading the RWW Section During Self-Programming27127.8.7 Setting the Boot Loader Lock Bits by SPM27127.8.8 EEPROM Write Prevents Writing to SPMCSR27127.8.9 Reading the Fuse and Lock Bits from Software27127.8.10 Reading the Signature Row from Software27227.8.11 Preventing Flash Corruption27327.8.12 Programming Time for Flash when Using SPM27327.8.13 Simple Assembly Code Example for a Boot Loader27327.8.14 ATmega88A and ATmega88PA Boot Loader Parameters27627.8.15 ATmega168A and ATmega168PA Boot Loader Parameters27727.8.16 ATmega328 and ATmega328P Boot Loader Parameters27827.9 Register Description27927.9.1 SPMCSR – Store Program Memory Control and Status Register27928. Memory Programming28128.1 Program And Data Memory Lock Bits28128.2 Fuse Bits28228.2.1 Latching of Fuses28528.3 Signature Bytes28528.4 Calibration Byte28528.5 Page Size28628.6 Parallel Programming Parameters, Pin Mapping, and Commands28628.6.1 Signal Names28628.7 Parallel Programming28828.7.1 Enter Programming Mode28828.7.2 Considerations for Efficient Programming28928.7.3 Chip Erase28928.7.4 Programming the Flash28928.7.5 Programming the EEPROM29128.7.6 Reading the Flash29228.7.7 Reading the EEPROM29228.7.8 Programming the Fuse Low Bits29328.7.9 Programming the Fuse High Bits29328.7.10 Programming the Extended Fuse Bits29328.7.11 Programming the Lock Bits29428.7.12 Reading the Fuse and Lock Bits29428.7.13 Reading the Signature Bytes29428.7.14 Reading the Calibration Byte29528.7.15 Parallel Programming Characteristics29528.8 Serial Downloading29528.8.1 Serial Programming Pin Mapping29628.8.2 Serial Programming Algorithm29628.8.3 Serial Programming Instruction set29728.8.4 SPI Serial Programming Characteristics29929. Electrical Characteristics – (TA = -40°C to 85°C)30029.1 Absolute Maximum Ratings*30029.2 DC Characteristics30029.2.1 ATmega48A DC Characteristics30229.2.2 ATmega48PA DC Characteristics – Current Consumption30229.2.3 ATmega88A DC Characteristics30329.2.4 ATmega88PA DC Characteristics30429.2.5 ATmega168A DC Characteristics30529.2.6 ATmega168PA DC Characteristics30529.2.7 ATmega328 DC Characteristics30629.2.8 ATmega328P DC Characteristics30729.3 Speed Grades30729.4 Clock Characteristics30929.4.1 Calibrated Internal RC Oscillator Accuracy30929.4.2 External Clock Drive Waveforms30929.4.3 External Clock Drive30929.5 System and Reset Characteristics31029.6 SPI Timing Characteristics31129.7 Two-wire Serial Interface Characteristics31329.8 ADC Characteristics31529.9 Parallel Programming Characteristics31630. Electrical Characteristics (TA = -40°C to 105°C)31830.1 Absolute Maximum Ratings*31830.2 DC Characteristics31830.2.1 ATmega48PA DC Characteristics – Current Consumption31930.2.2 ATmega88PA DC Characteristics – Current Consumption32030.2.3 ATmega168P DC Characteristics – Current Consumption32030.2.4 ATmega328P DC Characteristics – Current Consumption32131. Typical Characteristics – (TA = -40°C to 85°C)32231.1 ATmega48A Typical Characteristics32331.1.1 Active Supply Current32331.1.2 Idle Supply Current32531.1.3 ATmega48A: Supply Current of IO Modules32831.1.4 Power-down Supply Current32931.1.5 Power-save Supply Current33031.1.6 Standby Supply Current33031.1.7 Pin Pull-Up33131.1.8 Pin Driver Strength33431.1.9 Pin Threshold and Hysteresis33631.1.10 BOD Threshold33931.1.11 Internal Oscillator Speed34131.1.12 Current Consumption of Peripheral Units34331.1.13 Current Consumption in Reset and Reset Pulsewidth34631.2 ATmega48PA Typical Characteristics34831.2.1 Active Supply Current34831.2.2 Idle Supply Current35031.2.3 ATmega48PA: Supply Current of IO Modules35331.2.4 Power-down Supply Current35431.2.5 Power-save Supply Current35531.2.6 Standby Supply Current35531.2.7 Pin Pull-Up35631.2.8 Pin Driver Strength35931.2.9 Pin Threshold and Hysteresis36131.2.10 BOD Threshold36431.2.11 Internal Oscillator Speed36631.2.12 Current Consumption of Peripheral Units36831.2.13 Current Consumption in Reset and Reset Pulsewidth37131.3 ATmega88A Typical Characteristics37331.3.1 Active Supply Current37331.3.2 Idle Supply Current37531.3.3 ATmega88A: Supply Current of IO Modules37831.3.4 Power-down Supply Current37931.3.5 Power-save Supply Current38031.3.6 Standby Supply Current38031.3.7 Pin Pull-Up38131.3.8 Pin Driver Strength38431.3.9 Pin Threshold and Hysteresis38631.3.10 BOD Threshold38931.3.11 Internal Oscillator Speed39131.3.12 Current Consumption of Peripheral Units39331.3.13 Current Consumption in Reset and Reset Pulsewidth39631.4 ATmega88PA Typical Characteristics39731.4.1 Active Supply Current39731.4.2 Idle Supply Current40031.4.3 ATmega88PA: Supply Current of IO Modules40331.4.4 Power-down Supply Current40431.4.5 Power-save Supply Current40531.4.6 Standby Supply Current40531.4.7 Pin Pull-Up40631.4.8 Pin Driver Strength40931.4.9 Pin Threshold and Hysteresis41131.4.10 BOD Threshold41431.4.11 Internal Oscillator Speed41631.4.12 Current Consumption of Peripheral Units41931.4.13 Current Consumption in Reset and Reset Pulsewidth42131.5 ATmega168A Typical Characteristics42331.5.1 Active Supply Current42331.5.2 Idle Supply Current42531.5.3 ATmega168A Supply Current of IO Modules42831.5.4 Power-down Supply Current42931.5.5 Power-save Supply Current43031.5.6 Standby Supply Current43031.5.7 Pin Pull-Up43131.5.8 Pin Driver Strength43431.5.9 Pin Threshold and Hysteresis43631.5.10 BOD Threshold43931.5.11 Internal Oscillator Speed44131.5.12 Current Consumption of Peripheral Units44331.5.13 Current Consumption in Reset and Reset Pulsewidth44631.6 ATmega168PA Typical Characteristics44731.6.1 Active Supply Current44731.6.2 Idle Supply Current45031.6.3 ATmega168PA Supply Current of IO Modules45331.6.4 Power-down Supply Current45431.6.5 Power-save Supply Current45531.6.6 Standby Supply Current45531.6.7 Pin Pull-Up45631.6.8 Pin Driver Strength45931.6.9 Pin Threshold and Hysteresis46131.6.10 BOD Threshold46431.6.11 Internal Oscillator Speed46631.6.12 Current Consumption of Peripheral Units46931.6.13 Current Consumption in Reset and Reset Pulsewidth47131.7 ATmega328 Typical Characteristics47331.7.1 Active Supply Current47331.7.2 Idle Supply Current47531.7.3 ATmega328 Supply Current of IO Modules47831.7.4 Power-down Supply Current47931.7.5 Power-save Supply Current48031.7.6 Standby Supply Current48031.7.7 Pin Pull-Up48131.7.8 Pin Driver Strength48431.7.9 Pin Threshold and Hysteresis48631.7.10 BOD Threshold48931.7.11 Internal Oscillator Speed49131.7.12 Current Consumption of Peripheral Units49331.7.13 Current Consumption in Reset and Reset Pulsewidth49631.8 ATmega328P Typical Characteristics49731.8.1 Active Supply Current49731.8.2 Idle Supply Current50031.8.3 ATmega328P Supply Current of IO Modules50231.8.4 Power-down Supply Current50331.8.5 Power-save Supply Current50431.8.6 Standby Supply Current50531.8.7 Pin Pull-Up50531.8.8 Pin Driver Strength50831.8.9 Pin Threshold and Hysteresis51031.8.10 BOD Threshold51331.8.11 Internal Oscillator Speed51531.8.12 Current Consumption of Peripheral Units51831.8.13 Current Consumption in Reset and Reset Pulsewidth52032. ATmega48PA Typical Characteristics – (TA = -40°C to 105°C)52232.1 Active Supply Current52232.2 Idle Supply Current52532.3 Power-down Supply Current52732.4 Power-save Supply Current52832.5 Standby Supply Current52932.6 Pin Pull-Up52932.7 Pin Driver Strength53232.8 Pin Threshold and Hysteresis53432.9 BOD Threshold53732.10 Internal Oscillator Speed53932.11 Current Consumption of Peripheral Units54132.12 Current Consumption in Reset and Reset Pulsewidth54433. ATmega88PA Typical Characteristics – (TA = -40°C to 105°C)54633.1 Active Supply Current54633.2 Idle Supply Current54933.3 Power-down Supply Current55133.4 Power-save Supply Current55233.5 Pin Pull-Up55333.6 Pin Driver Strength55633.7 Pin Threshold and Hysteresis55833.8 BOD Threshold56133.9 Internal Oscillator Speed56233.10 Current Consumption of Peripheral Units56533.11 Current Consumption in Reset and Reset Pulsewidth56734. ATmega168PA Typical Characteristics – (TA = -40°C to 105°C)57034.1 Active Supply Current57034.2 Idle Supply Current57334.3 Power-down Supply Current57534.4 Power-save Supply Current57634.5 Standby Supply Current57734.6 Pin Pull-Up57734.7 Pin Driver Strength58034.8 Pin Threshold and Hysteresis58234.9 BOD Threshold58534.10 Internal Oscillator Speed58834.11 Current Consumption of Peripheral Units59034.12 Current Consumption in Reset and Reset Pulsewidth59335. ATmega328P Typical Characteristics – (TA = -40°C to 105°C)59535.1 ATmega328P Active Supply Current59535.2 Idle Supply Current59835.3 Power-down Supply Current60035.4 Power-save Supply Current60135.5 Standby Supply Current60235.6 Pin Pull-Up60235.7 Pin Driver Strength60535.8 Pin Threshold and Hysteresis60735.9 BOD Threshold61035.10 Internal Oscillator Speed61235.11 Current Consumption of Peripheral Units61535.12 Current Consumption in Reset and Reset Pulsewidth61736. Register Summary61937. Instruction Set Summary62338. Ordering Information62638.1 ATmega48A62638.2 ATmega48PA62738.3 ATmega88A62838.4 ATmega88PA62938.5 ATmega168A63038.6 ATmega168PA63138.7 ATmega32863238.8 ATmega328P63339. Packaging Information63439.1 32A63439.2 32CC163539.3 28M163639.4 32M1-A63739.5 28P363840. Errata63940.1 Errata ATmega48A63940.1.1 Rev. D63940.2 Errata ATmega48PA63940.2.1 Rev. A63940.2.2 Rev. D63940.3 Errata ATmega88A64040.3.1 Rev. F64040.4 Errata ATmega88PA64040.4.1 Rev. F64040.4.2 Rev. A64140.5 Errata ATmega168A64140.5.1 Rev. E64140.6 Errata ATmega168PA64140.6.1 Rev E64240.7 Errata ATmega32864340.7.1 Rev D64340.7.2 Rev C64340.7.3 Rev B64340.7.4 Rev A64340.8 Errata ATmega328P64440.8.1 Rev D64440.8.2 Rev C64440.8.3 Rev B64440.8.4 Rev A64541. Datasheet Revision History64641.1 Rev. 8271H – 08/201364641.2 Rev. 8271G – 02/201364641.3 Rev. 8271F – 08/201264641.4 Rev. 8271E – 07/201264741.5 Rev. 8271D – 05/1164741.6 Rev. 8271C – 08/1064741.7 Rev. 8271B – 04/1064841.8 Rev. 8271A – 12/09648Dimensioni: 31,3 MBPagine: 657Language: EnglishApri il manuale
