Manuali utente per Freescale Semiconductor MC68HC908MR32

Sommario

• Revision History

  4
• List of Chapters

  5
• Table of Contents

  7
• Chapter 1 General Description

  17
  • 1.1 Introduction

    17
  • 1.2 Features

    17
  • 1.3 MCU Block Diagram

    18
  • 1.4 Pin Assignments

    20
    • 1.4.1 Power Supply Pins (VDD and VSS)

      22
    • 1.4.2 Oscillator Pins (OSC1 and OSC2)

      22
    • 1.4.3 External Reset Pin (RST)

      22
    • 1.4.4 External Interrupt Pin (IRQ)

      22
    • 1.4.5 CGM Power Supply Pins (VDDA and VSSAD)

      22
    • 1.4.6 External Filter Capacitor Pin (CGMXFC)

      23
    • 1.4.7 Analog Power Supply Pins (VDDAD and VSSAD)

      23
    • 1.4.8 ADC Voltage Decoupling Capacitor Pin (VREFH)

      23
    • 1.4.9 ADC Voltage Reference Low Pin (VREFL)

      23
    • 1.4.10 Port A Input/Output (I/O) Pins (PTA7-PTA0)

      23
    • 1.4.11 Port B I/O Pins (PTB7/ATD7-PTB0/ATD0)

      23
    • 1.4.12 Port C I/O Pins (PTC6-PTC2 and PTC1/ATD9-PTC0/ATD8)

      23
    • 1.4.13 Port D Input-Only Pins (PTD6/IS3-PTD4/IS1 and PTD3/FAULT4-PTD0/FAULT1)

      23
    • 1.4.14 PWM Pins (PWM6-PWM1)

      23
    • 1.4.15 PWM Ground Pin (PWMGND)

      24
    • 1.4.16 Port E I/O Pins (PTE7/TCH3A-PTE3/TCLKA and PTE2/TCH1B-PTE0/TCLKB)

      24
    • 1.4.17 Port F I/O Pins (PTF5/TxD-PTF4/RxD and PTF3/MISO-PTF0/SPSCK)

      24
• Chapter 2 Memory

  25
  • 2.1 Introduction

    25
  • 2.2 Unimplemented Memory Locations

    25
  • 2.3 Reserved Memory Locations

    25
  • 2.4 I/O Section

    26
  • 2.5 Memory Map

    26
  • 2.6 Monitor ROM

    37
  • 2.7 Random-Access Memory (RAM)

    37
  • 2.8 FLASH Memory (FLASH)

    38
    • 2.8.1 FLASH Control Register

      38
    • 2.8.2 FLASH Page Erase Operation

      39
    • 2.8.3 FLASH Mass Erase Operation

      40
    • 2.8.4 FLASH Program Operation

      41
    • 2.8.5 FLASH Block Protection

      43
    • 2.8.6 FLASH Block Protect Register

      43
    • 2.8.7 Wait Mode

      44
    • 2.8.8 Stop Mode

      44
• Chapter 3 Analog-to-Digital Converter (ADC)

  45
  • 3.1 Introduction

    45
  • 3.2 Features

    45
  • 3.3 Functional Description

    45
    • 3.3.1 ADC Port I/O Pins

      47
    • 3.3.2 Voltage Conversion

      47
    • 3.3.3 Conversion Time

      48
    • 3.3.4 Continuous Conversion

      48
    • 3.3.5 Result Justification

      48
    • 3.3.6 Monotonicity

      49
  • 3.4 Interrupts

    50
  • 3.5 Wait Mode

    50
  • 3.6 I/O Signals

    50
    • 3.6.1 ADC Analog Power Pin (VDDAD)

      50
    • 3.6.2 ADC Analog Ground Pin (VSSAD)

      50
    • 3.6.3 ADC Voltage Reference Pin (VREFH)

      50
    • 3.6.4 ADC Voltage Reference Low Pin (VREFL)

      50
    • 3.6.5 ADC Voltage In (ADVIN)

      51
    • 3.6.6 ADC External Connections

      51
      • 3.6.6.1 VREFH and VREFL

        51
      • 3.6.6.2 ANx

        51
      • 3.6.6.3 Grounding

        51
  • 3.7 I/O Registers

    51
    • 3.7.1 ADC Status and Control Register

      52
    • 3.7.2 ADC Data Register High

      54
    • 3.7.3 ADC Data Register Low

      54
    • 3.7.4 ADC Clock Register

      55
• Chapter 4 Clock Generator Module (CGM)

  57
  • 4.1 Introduction

    57
  • 4.2 Features

    57
  • 4.3 Functional Description

    57
    • 4.3.1 Crystal Oscillator Circuit

      59
    • 4.3.2 Phase-Locked Loop Circuit (PLL)

      59
      • 4.3.2.1 PLL Circuits

        59
      • 4.3.2.2 Acquisition and Tracking Modes

        60
      • 4.3.2.3 Manual and Automatic PLL Bandwidth Modes

        60
      • 4.3.2.4 Programming the PLL

        61
      • 4.3.2.5 Special Programming Exceptions

        62
    • 4.3.3 Base Clock Selector Circuit

      62
    • 4.3.4 CGM External Connections

      63
  • 4.4 I/O Signals

    64
    • 4.4.1 Crystal Amplifier Input Pin (OSC1)

      64
    • 4.4.2 Crystal Amplifier Output Pin (OSC2)

      64
    • 4.4.3 External Filter Capacitor Pin (CGMXFC)

      64
    • 4.4.4 PLL Analog Power Pin (VDDA)

      64
    • 4.4.5 Oscillator Enable Signal (SIMOSCEN)

      64
    • 4.4.6 Crystal Output Frequency Signal (CGMXCLK)

      65
    • 4.4.7 CGM Base Clock Output (CGMOUT)

      65
    • 4.4.8 CGM CPU Interrupt (CGMINT)

      65
  • 4.5 CGM Registers

    65
    • 4.5.1 PLL Control Register

      66
    • 4.5.2 PLL Bandwidth Control Register

      67
    • 4.5.3 PLL Programming Register

      68
  • 4.6 Interrupts

    69
  • 4.7 Wait Mode

    69
  • 4.8 Acquisition/Lock Time Specifications

    70
    • 4.8.1 Acquisition/Lock Time Definitions

      70
    • 4.8.2 Parametric Influences on Reaction Time

      70
    • 4.8.3 Choosing a Filter Capacitor

      71
    • 4.8.4 Reaction Time Calculation

      71
• Chapter 5 Configuration Register (CONFIG)

  73
  • 5.1 Introduction

    73
  • 5.2 Functional Description

    73
  • 5.3 Configuration Register

    74
• Chapter 6 Computer Operating Properly (COP)

  75
  • 6.1 Introduction

    75
  • 6.2 Functional Description

    75
  • 6.3 I/O Signals

    76
    • 6.3.1 CGMXCLK

      76
    • 6.3.2 COPCTL Write

      76
    • 6.3.3 Power-On Reset

      76
    • 6.3.4 Internal Reset

      76
    • 6.3.5 Reset Vector Fetch

      76
    • 6.3.6 COPD (COP Disable)

      77
  • 6.4 COP Control Register

    77
  • 6.5 Interrupts

    77
  • 6.6 Monitor Mode

    77
  • 6.7 Wait Mode

    77
  • 6.8 Stop Mode

    77
• Chapter 7 Central Processor Unit (CPU)

  79
  • 7.1 Introduction

    79
  • 7.2 Features

    79
  • 7.3 CPU Registers

    79
    • 7.3.1 Accumulator

      80
    • 7.3.2 Index Register

      80
    • 7.3.3 Stack Pointer

      81
    • 7.3.4 Program Counter

      81
    • 7.3.5 Condition Code Register

      82
  • 7.4 Arithmetic/Logic Unit (ALU)

    83
  • 7.5 Low-Power Modes

    83
    • 7.5.1 Wait Mode

      83
    • 7.5.2 Stop Mode

      83
  • 7.6 CPU During Break Interrupts

    83
  • 7.7 Instruction Set Summary

    84
  • 7.8 Opcode Map

    89
• Chapter 8 External Interrupt (IRQ)

  91
  • 8.1 Introduction

    91
  • 8.2 Features

    91
  • 8.3 Functional Description

    91
  • 8.4 IRQ Pin

    92
  • 8.5 IRQ Status and Control Register

    94
• Chapter 9 Low-Voltage Inhibit (LVI)

  97
  • 9.1 Introduction

    97
  • 9.2 Features

    97
  • 9.3 Functional Description

    97
    • 9.3.1 Polled LVI Operation

      98
    • 9.3.2 Forced Reset Operation

      98
    • 9.3.3 False Reset Protection

      98
    • 9.3.4 LVI Trip Selection

      98
  • 9.4 LVI Status and Control Register

    99
  • 9.5 LVI Interrupts

    99
  • 9.6 Wait Mode

    99
  • 9.7 Stop Mode

    100
• Chapter 10 Input/Output (I/O) Ports (PORTS)

  101
  • 10.1 Introduction

    101
  • 10.2 Port A

    103
    • 10.2.1 Port A Data Register

      103
    • 10.2.2 Data Direction Register A

      103
  • 10.3 Port B

    104
    • 10.3.1 Port B Data Register

      104
    • 10.3.2 Data Direction Register B

      105
  • 10.4 Port C

    106
    • 10.4.1 Port C Data Register

      106
    • 10.4.2 Data Direction Register C

      106
  • 10.5 Port D

    107
  • 10.6 Port E

    108
    • 10.6.1 Port E Data Register

      108
    • 10.6.2 Data Direction Register E

      109
  • 10.7 Port F

    110
    • 10.7.1 Port F Data Register

      110
    • 10.7.2 Data Direction Register F

      110
• Chapter 11 Power-On Reset (POR)

  113
  • 11.1 Introduction

    113
  • 11.2 Functional Description

    113
• Chapter 12 Pulse-Width Modulator for Motor Control (PWMMC)

  115
  • 12.1 Introduction

    115
  • 12.2 Features

    115
  • 12.3 Timebase

    120
    • 12.3.1 Resolution

      120
    • 12.3.2 Prescaler

      122
  • 12.4 PWM Generators

    122
    • 12.4.1 Load Operation

      122
    • 12.4.2 PWM Data Overflow and Underflow Conditions

      125
  • 12.5 Output Control

    126
    • 12.5.1 Selecting Six Independent PWMs or Three Complementary PWM Pairs

      126
    • 12.5.2 Dead-Time Insertion

      127
    • 12.5.3 Top/Bottom Correction with Motor Phase Current Polarity Sensing

      130
    • 12.5.4 Output Polarity

      133
    • 12.5.5 PWM Output Port Control

      135
  • 12.6 Fault Protection

    137
    • 12.6.1 Fault Condition Input Pins

      137
      • 12.6.1.1 Fault Pin Filter

        139
      • 12.6.1.2 Automatic Mode

        139
      • 12.6.1.3 Manual Mode

        140
    • 12.6.2 Software Output Disable

      141
    • 12.6.3 Output Port Control

      141
  • 12.7 Initialization and the PWMEN Bit

    142
  • 12.8 PWM Operation in Wait Mode

    143
  • 12.9 Control Logic Block

    143
    • 12.9.1 PWM Counter Registers

      143
    • 12.9.2 PWM Counter Modulo Registers

      144
    • 12.9.3 PWMx Value Registers

      145
    • 12.9.4 PWM Control Register 1

      146
    • 12.9.5 PWM Control Register 2

      148
    • 12.9.6 Dead-Time Write-Once Register

      150
    • 12.9.7 PWM Disable Mapping Write-Once Register

      150
    • 12.9.8 Fault Control Register

      150
    • 12.9.9 Fault Status Register

      152
    • 12.9.10 Fault Acknowledge Register

      153
    • 12.9.11 PWM Output Control Register

      154
  • 12.10 PWM Glossary

    155
• Chapter 13 Serial Communications Interface Module (SCI)

  157
  • 13.1 Introduction

    157
  • 13.2 Features

    157
  • 13.3 Functional Description

    159
    • 13.3.1 Data Format

      160
    • 13.3.2 Transmitter

      161
      • 13.3.2.1 Character Length

        162
      • 13.3.2.2 Character Transmission

        162
      • 13.3.2.3 Break Characters

        162
      • 13.3.2.4 Idle Characters

        163
      • 13.3.2.5 Inversion of Transmitted Output

        163
      • 13.3.2.6 Transmitter Interrupts

        163
    • 13.3.3 Receiver

      163
      • 13.3.3.1 Character Length

        164
      • 13.3.3.2 Character Reception

        165
      • 13.3.3.3 Data Sampling

        165
      • 13.3.3.4 Framing Errors

        167
      • 13.3.3.5 Receiver Wakeup

        167
      • 13.3.3.6 Receiver Interrupts

        167
      • 13.3.3.7 Error Interrupts

        167
  • 13.4 Wait Mode

    168
  • 13.5 SCI During Break Module Interrupts

    168
  • 13.6 I/O Signals

    168
    • 13.6.1 PTF5/TxD (Transmit Data)

      168
    • 13.6.2 PTF4/RxD (Receive Data)

      169
  • 13.7 I/O Registers

    169
    • 13.7.1 SCI Control Register 1

      169
    • 13.7.2 SCI Control Register 2

      171
    • 13.7.3 SCI Control Register 3

      173
    • 13.7.4 SCI Status Register 1

      174
    • 13.7.5 SCI Status Register 2

      176
    • 13.7.6 SCI Data Register

      177
    • 13.7.7 SCI Baud Rate Register

      177
• Chapter 14 System Integration Module (SIM)

  181
  • 14.1 Introduction

    181
  • 14.2 SIM Bus Clock Control and Generation

    182
    • 14.2.1 Bus Timing

      182
    • 14.2.2 Clock Startup from POR or LVI Reset

      182
    • 14.2.3 Clocks in Wait Mode

      183
  • 14.3 Reset and System Initialization

    183
    • 14.3.1 External Pin Reset

      183
    • 14.3.2 Active Resets from Internal Sources

      184
      • 14.3.2.1 Power-On Reset (POR)

        185
      • 14.3.2.2 Computer Operating Properly (COP) Reset

        185
      • 14.3.2.3 Illegal Opcode Reset

        186
      • 14.3.2.4 Illegal Address Reset

        186
      • 14.3.2.5 Forced Monitor Mode Entry Reset (MENRST)

        186
      • 14.3.2.6 Low-Voltage Inhibit (LVI) Reset

        186
  • 14.4 SIM Counter

    186
    • 14.4.1 SIM Counter During Power-On Reset

      186
    • 14.4.2 SIM Counter and Reset States

      186
  • 14.5 Exception Control

    187
    • 14.5.1 Interrupts

      187
      • 14.5.1.1 Hardware Interrupts

        189
      • 14.5.1.2 Software Interrupt (SWI) Instruction

        190
    • 14.5.2 Reset

      190
  • 14.6 Low-Power Mode

    190
    • 14.6.1 Wait Mode

      190
    • 14.6.2 Stop Mode

      191
  • 14.7 SIM Registers

    191
    • 14.7.1 SIM Break Status Register

      191
    • 14.7.2 SIM Reset Status Register

      192
    • 14.7.3 SIM Break Flag Control Register

      193
• Chapter 15 Serial Peripheral Interface Module (SPI)

  195
  • 15.1 Introduction

    195
  • 15.2 Features

    195
  • 15.3 Pin Name Conventions

    195
  • 15.4 Functional Description

    197
    • 15.4.1 Master Mode

      198
    • 15.4.2 Slave Mode

      199
  • 15.5 Transmission Formats

    199
    • 15.5.1 Clock Phase and Polarity Controls

      199
    • 15.5.2 Transmission Format When CPHA = 0

      200
    • 15.5.3 Transmission Format When CPHA = 1

      201
    • 15.5.4 Transmission Initiation Latency

      201
  • 15.6 Error Conditions

    203
    • 15.6.1 Overflow Error

      203
    • 15.6.2 Mode Fault Error

      204
  • 15.7 Interrupts

    206
  • 15.8 Resetting the SPI

    207
  • 15.9 Queuing Transmission Data

    207
  • 15.10 Low-Power Mode

    208
  • 15.11 I/O Signals

    208
    • 15.11.1 MISO (Master In/Slave Out)

      209
    • 15.11.2 MOSI (Master Out/Slave In)

      209
    • 15.11.3 SPSCK (Serial Clock)

      209
    • 15.11.4 SS (Slave Select)

      209
    • 15.11.5 VSS (Clock Ground)

      210
  • 15.12 I/O Registers

    210
    • 15.12.1 SPI Control Register

      210
    • 15.12.2 SPI Status and Control Register

      212
    • 15.12.3 SPI Data Register

      214
• Chapter 16 Timer Interface A (TIMA)

  215
  • 16.1 Introduction

    215
  • 16.2 Features

    215
  • 16.3 Functional Description

    219
    • 16.3.1 TIMA Counter Prescaler

      219
    • 16.3.2 Input Capture

      219
    • 16.3.3 Output Compare

      220
      • 16.3.3.1 Unbuffered Output Compare

        220
      • 16.3.3.2 Buffered Output Compare

        221
    • 16.3.4 Pulse-Width Modulation (PWM)

      221
      • 16.3.4.1 Unbuffered PWM Signal Generation

        222
      • 16.3.4.2 Buffered PWM Signal Generation

        223
      • 16.3.4.3 PWM Initialization

        223
  • 16.4 Interrupts

    224
  • 16.5 Wait Mode

    224
  • 16.6 I/O Signals

    225
    • 16.6.1 TIMA Clock Pin (PTE3/TCLKA)

      225
    • 16.6.2 TIMA Channel I/O Pins (PTE4/TCH0A-PTE7/TCH3A)

      225
  • 16.7 I/O Registers

    225
    • 16.7.1 TIMA Status and Control Register

      225
    • 16.7.2 TIMA Counter Registers

      227
    • 16.7.3 TIMA Counter Modulo Registers

      228
    • 16.7.4 TIMA Channel Status and Control Registers

      228
    • 16.7.5 TIMA Channel Registers

      232
• Chapter 17 Timer Interface B (TIMB)

  235
  • 17.1 Introduction

    235
  • 17.2 Features

    235
  • 17.3 Functional Description

    235
    • 17.3.1 TIMB Counter Prescaler

      238
    • 17.3.2 Input Capture

      238
    • 17.3.3 Output Compare

      239
      • 17.3.3.1 Unbuffered Output Compare

        239
      • 17.3.3.2 Buffered Output Compare

        240
    • 17.3.4 Pulse-Width Modulation (PWM)

      240
      • 17.3.4.1 Unbuffered PWM Signal Generation

        241
      • 17.3.4.2 Buffered PWM Signal Generation

        241
      • 17.3.4.3 PWM Initialization

        242
  • 17.4 Interrupts

    243
  • 17.5 Wait Mode

    243
  • 17.6 I/O Signals

    243
    • 17.6.1 TIMB Clock Pin (PTE0/TCLKB)

      243
    • 17.6.2 TIMB Channel I/O Pins (PTE1/TCH0B-PTE2/TCH1B)

      243
  • 17.7 I/O Registers

    244
    • 17.7.1 TIMB Status and Control Register

      244
    • 17.7.2 TIMB Counter Registers

      246
    • 17.7.3 TIMB Counter Modulo Registers

      246
    • 17.7.4 TIMB Channel Status and Control Registers

      247
    • 17.7.5 TIMB Channel Registers

      250
• Chapter 18 Development Support

  251
  • 18.1 Introduction

    251
  • 18.2 Break Module (BRK)

    251
    • 18.2.1 Functional Description

      251
      • 18.2.1.1 Flag Protection During Break Interrupts

        251
      • 18.2.1.2 CPU During Break Interrupts

        253
      • 18.2.1.3 TIM1 and TIM2 During Break Interrupts

        253
      • 18.2.1.4 COP During Break Interrupts

        253
    • 18.2.2 Low-Power Modes

      253
      • 18.2.2.1 Wait Mode

        253
      • 18.2.2.2 Stop Mode

        253
    • 18.2.3 Break Module Registers

      253
      • 18.2.3.1 Break Status and Control Register

        254
      • 18.2.3.2 Break Address Registers

        254
      • 18.2.3.3 Break Status Register

        255
      • 18.2.3.4 TBreak Flag Control Register

        255
  • 18.3 Monitor ROM (MON)

    255
    • 18.3.1 Functional Description

      256
      • 18.3.1.1 Entering Monitor Mode

        256
      • 18.3.1.2 Normal Monitor Mode

        256
      • 18.3.1.3 Forced Monitor Mode

        259
      • 18.3.1.4 Data Format

        259
      • 18.3.1.5 Echoing

        260
      • 18.3.1.6 Break Signal

        260
      • 18.3.1.7 Commands

        260
      • 18.3.1.8 Baud Rate

        263
    • 18.3.2 Security

      263
• Chapter 19 Electrical Specifications

  265
  • 19.1 Introduction

    265
  • 19.2 Absolute Maximum Ratings

    265
  • 19.3 Functional Operating Range

    266
  • 19.4 Thermal Characteristics

    266
  • 19.5 DC Electrical Characteristics

    267
  • 19.6 FLASH Memory Characteristics

    268
  • 19.7 Control Timing

    268
  • 19.8 Serial Peripheral Interface Characteristics

    269
  • 19.9 TImer Interface Module Characteristics

    272
  • 19.10 Clock Generation Module Component Specifications

    272
  • 19.11 CGM Operating Conditions

    272
  • 19.12 CGM Acquisition/Lock Time Specifications

    273
  • 19.13 Analog-to-Digital Converter (ADC) Characteristics

    274
• Chapter 20 Ordering Information and Mechanical Specifications

  275
  • 20.1 Introduction

    275
  • 20.2 Order Numbers

    275
  • 20.3 64-Pin Plastic Quad Flat Pack (QFP)

    276
  • 20.4 56-Pin Shrink Dual In-Line Package (SDIP)

    277
• Appendix A MC68HC908MR16

  279