Scheda Tecnica (S26361-F3476-E321)SommarioContents4Figures6Tables7Revision History8Quad-Core Intel Xeon Processor 3200 Series Features9Quad-Core Intel® Xeon® Processor 3200 Series11 Introduction111.1 Terminology111.1.1 Processor Terminology121.2 References13Table 1-1. References132 Electrical Specifications152.1 Power and Ground Lands152.2 Decoupling Guidelines152.2.1 VCC Decoupling152.2.2 VTT Decoupling152.2.3 FSB Decoupling162.3 Voltage Identification16Table 2-1. Voltage Identification Definition172.4 Reserved, Unused, and TESTHI Signals182.5 Voltage and Current Specification192.5.1 Absolute Maximum and Minimum Ratings19Table 2-2. Absolute Maximum and Minimum Ratings192.5.2 DC Voltage and Current Specification20Table 2-3. Voltage and Current Specifications20Table 2-4. VCC Static and Transient Tolerance21Figure 2-1. VCC Static and Transient Tolerance222.5.3 VCC Overshoot22Table 2-5. VCC Overshoot Specifications22Figure 2-2. VCC Overshoot Example Waveform232.5.4 Die Voltage Validation232.6 Signaling Specifications232.6.1 FSB Signal Groups24Table 2-6. FSB Signal Groups24Table 2-7. Signal Characteristics25Table 2-8. Signal Reference Voltages252.6.2 CMOS and Open Drain Signals252.6.3 Processor DC Specifications26Table 2-9. GTL+ Signal Group DC Specifications26Table 2-10. Open Drain and TAP Output Signal Group DC Specifications26Table 2-11. CMOS Signal Group DC Specifications27Table 2-12. PECI DC Electrical Limits272.6.3.1 GTL+ Front Side Bus Specifications28Table 2-13. GTL+ Bus Voltage Definitions282.7 Clock Specifications282.7.1 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking28Table 2-14. Core Frequency to FSB Multiplier Configuration282.7.2 FSB Frequency Select Signals (BSEL[2:0])29Table 2-15. BSEL[2:0] Frequency Table for BCLK[1:0]292.7.3 Phase Lock Loop (PLL) and Filter292.7.4 BCLK[1:0] Specifications30Table 2-16. Front Side Bus Differential BCLK Specifications30Table 2-17. FSB Differential Clock Specifications (1066 MHz FSB)30Figure 2-3. Differential Clock Waveform31Figure 2-4. Differential Clock Crosspoint Specification31Figure 2-5. Differential Measurements313 Package Mechanical Specifications33Figure 3-1. Processor Package Assembly Sketch333.1 Package Mechanical Drawing33Figure 3-2. Processor Package Drawing Sheet 1 of 335Figure 3-3. Processor Package Drawing Sheet 2 of 336Figure 3-4. Processor Package Drawing Sheet 3 of 3373.2 Processor Component Keep-Out Zones383.3 Package Loading Specifications38Table 3-1. Processor Loading Specifications383.4 Package Handling Guidelines38Table 3-2. Package Handling Guidelines383.5 Package Insertion Specifications393.6 Processor Mass Specification393.7 Processor Materials39Table 3-3. Processor Materials393.8 Processor Markings39Figure 3-5. Processor Top-Side Marking Example393.9 Processor Land Coordinates40Figure 3-6. Processor Land Coordinates and Quadrants (Top View)404 Land Listing and Signal Descriptions414.1 Processor Land Assignments41Figure 4-1. land-out Diagram (Top View - Left Side)42Figure 4-2. land-out Diagram (Top View - Right Side)43Table 4-1. Alphabetical Land Assignments (Sheet 1 of 21)44Table 4-2. Numerical Land Assignment (Sheet 1 of 21)554.2 Alphabetical Signals Reference66Table 4-3. Signal Description (Sheet 1 of 6)665 Thermal Specifications and Design Considerations735.1 Processor Thermal Specifications735.1.1 Thermal Specifications73Table 5-1. Processor Thermal Specifications74Table 5-2. Thermal Profile for 105 W Processor75Figure 5-1. Thermal Profile for 105 W Processor755.1.2 Thermal Metrology76Figure 5-2. Case Temperature (TC) Measurement Location765.2 Processor Thermal Features765.2.1 Thermal Monitor765.2.2 Thermal Monitor 277Figure 5-3. Thermal Monitor 2 Frequency and Voltage Ordering785.2.3 On-Demand Mode785.2.4 PROCHOT# Signal795.2.5 THERMTRIP# Signal795.3 Platform Environment Control Interface (PECI)805.3.1 Introduction805.3.1.1 Key Difference with Legacy Diode-Based Thermal Management80Figure 5-4. Conceptual Fan Control on PECI-Based Platforms805.3.2 PECI Specifications815.3.2.1 PECI Device Address815.3.2.2 PECI Command Support815.3.2.3 PECI Fault Handling Requirements815.3.2.4 PECI GetTemp0() and GetTemp1() Error Code Support81Table 5-3. GetTemp0() and GetTemp1() Error Codes816 Features836.1 Power-On Configuration Options83Table 6-1. Power-On Configuration Option Signals836.2 Clock Control and Low Power States83Figure 6-1. Processor Low Power State Machine846.2.1 Normal State846.2.2 HALT and Extended HALT Powerdown States846.2.2.1 HALT Powerdown State846.2.2.2 Extended HALT Powerdown State856.2.3 Stop Grant State856.2.4 Extended HALT Snoop or HALT Snoop State, Stop Grant Snoop State866.2.4.1 HALT Snoop State, Stop Grant Snoop State866.2.4.2 Extended HALT Snoop State867 Boxed Processor Specifications87Figure 7-1. Mechanical Representation of the Boxed Processor877.1 Mechanical Specifications887.1.1 Boxed Processor Cooling Solution Dimensions88Figure 7-2. Space Requirements for the Boxed Processor (Side View)88Figure 7-3. Space Requirements for the Boxed Processor (Top View)89Figure 7-4. Space Requirements for the Boxed Processor (Overall View)897.1.2 Boxed Processor Fan Heatsink Weight897.1.3 Boxed Processor Retention Mechanism and Heatsink Attach Clip Assembly907.2 Electrical Requirements907.2.1 Fan Heatsink Power Supply90Figure 7-5. Boxed Processor Fan Heatsink Power Cable Connector Description90Table 7-1. Fan Heatsink Power and Signal Specifications91Figure 7-6. Baseboard Power Header Placement Relative to Processor Socket917.3 Thermal Specifications917.3.1 Boxed Processor Cooling Requirements91Figure 7-7. Boxed Processor Fan Heatsink Airspace Keepout Requirements (Side 1 View)92Figure 7-8. Boxed Processor Fan Heatsink Airspace Keepout Requirements (Side 2 View)937.3.2 Fan Speed Control Operation938 Debug Tools Specifications958.1 Logic Analyzer Interface (LAI)958.1.1 Mechanical Considerations958.1.2 Electrical Considerations95Dimensioni: 1,37 MBPagine: 96Language: EnglishApri il manuale
Scheda Tecnica (S26361-F3239-E321)SommarioContents4Figures6Tables7Revision History8Quad-Core Intel Xeon Processor 3200 Series Features9Quad-Core Intel® Xeon® Processor 3200 Series11 Introduction111.1 Terminology111.1.1 Processor Terminology121.2 References13Table 1-1. References132 Electrical Specifications152.1 Power and Ground Lands152.2 Decoupling Guidelines152.2.1 VCC Decoupling152.2.2 VTT Decoupling152.2.3 FSB Decoupling162.3 Voltage Identification16Table 2-1. Voltage Identification Definition172.4 Reserved, Unused, and TESTHI Signals182.5 Voltage and Current Specification192.5.1 Absolute Maximum and Minimum Ratings19Table 2-2. Absolute Maximum and Minimum Ratings192.5.2 DC Voltage and Current Specification20Table 2-3. Voltage and Current Specifications20Table 2-4. VCC Static and Transient Tolerance21Figure 2-1. VCC Static and Transient Tolerance222.5.3 VCC Overshoot22Table 2-5. VCC Overshoot Specifications22Figure 2-2. VCC Overshoot Example Waveform232.5.4 Die Voltage Validation232.6 Signaling Specifications232.6.1 FSB Signal Groups24Table 2-6. FSB Signal Groups24Table 2-7. Signal Characteristics25Table 2-8. Signal Reference Voltages252.6.2 CMOS and Open Drain Signals252.6.3 Processor DC Specifications26Table 2-9. GTL+ Signal Group DC Specifications26Table 2-10. Open Drain and TAP Output Signal Group DC Specifications26Table 2-11. CMOS Signal Group DC Specifications27Table 2-12. PECI DC Electrical Limits272.6.3.1 GTL+ Front Side Bus Specifications28Table 2-13. GTL+ Bus Voltage Definitions282.7 Clock Specifications282.7.1 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking28Table 2-14. Core Frequency to FSB Multiplier Configuration282.7.2 FSB Frequency Select Signals (BSEL[2:0])29Table 2-15. BSEL[2:0] Frequency Table for BCLK[1:0]292.7.3 Phase Lock Loop (PLL) and Filter292.7.4 BCLK[1:0] Specifications30Table 2-16. Front Side Bus Differential BCLK Specifications30Table 2-17. FSB Differential Clock Specifications (1066 MHz FSB)30Figure 2-3. Differential Clock Waveform31Figure 2-4. Differential Clock Crosspoint Specification31Figure 2-5. Differential Measurements313 Package Mechanical Specifications33Figure 3-1. Processor Package Assembly Sketch333.1 Package Mechanical Drawing33Figure 3-2. Processor Package Drawing Sheet 1 of 335Figure 3-3. Processor Package Drawing Sheet 2 of 336Figure 3-4. Processor Package Drawing Sheet 3 of 3373.2 Processor Component Keep-Out Zones383.3 Package Loading Specifications38Table 3-1. Processor Loading Specifications383.4 Package Handling Guidelines38Table 3-2. Package Handling Guidelines383.5 Package Insertion Specifications393.6 Processor Mass Specification393.7 Processor Materials39Table 3-3. Processor Materials393.8 Processor Markings39Figure 3-5. Processor Top-Side Marking Example393.9 Processor Land Coordinates40Figure 3-6. Processor Land Coordinates and Quadrants (Top View)404 Land Listing and Signal Descriptions414.1 Processor Land Assignments41Figure 4-1. land-out Diagram (Top View - Left Side)42Figure 4-2. land-out Diagram (Top View - Right Side)43Table 4-1. Alphabetical Land Assignments (Sheet 1 of 21)44Table 4-2. Numerical Land Assignment (Sheet 1 of 21)554.2 Alphabetical Signals Reference66Table 4-3. Signal Description (Sheet 1 of 6)665 Thermal Specifications and Design Considerations735.1 Processor Thermal Specifications735.1.1 Thermal Specifications73Table 5-1. Processor Thermal Specifications74Table 5-2. Thermal Profile for 105 W Processor75Figure 5-1. Thermal Profile for 105 W Processor755.1.2 Thermal Metrology76Figure 5-2. Case Temperature (TC) Measurement Location765.2 Processor Thermal Features765.2.1 Thermal Monitor765.2.2 Thermal Monitor 277Figure 5-3. Thermal Monitor 2 Frequency and Voltage Ordering785.2.3 On-Demand Mode785.2.4 PROCHOT# Signal795.2.5 THERMTRIP# Signal795.3 Platform Environment Control Interface (PECI)805.3.1 Introduction805.3.1.1 Key Difference with Legacy Diode-Based Thermal Management80Figure 5-4. Conceptual Fan Control on PECI-Based Platforms805.3.2 PECI Specifications815.3.2.1 PECI Device Address815.3.2.2 PECI Command Support815.3.2.3 PECI Fault Handling Requirements815.3.2.4 PECI GetTemp0() and GetTemp1() Error Code Support81Table 5-3. GetTemp0() and GetTemp1() Error Codes816 Features836.1 Power-On Configuration Options83Table 6-1. Power-On Configuration Option Signals836.2 Clock Control and Low Power States83Figure 6-1. Processor Low Power State Machine846.2.1 Normal State846.2.2 HALT and Extended HALT Powerdown States846.2.2.1 HALT Powerdown State846.2.2.2 Extended HALT Powerdown State856.2.3 Stop Grant State856.2.4 Extended HALT Snoop or HALT Snoop State, Stop Grant Snoop State866.2.4.1 HALT Snoop State, Stop Grant Snoop State866.2.4.2 Extended HALT Snoop State867 Boxed Processor Specifications87Figure 7-1. Mechanical Representation of the Boxed Processor877.1 Mechanical Specifications887.1.1 Boxed Processor Cooling Solution Dimensions88Figure 7-2. Space Requirements for the Boxed Processor (Side View)88Figure 7-3. Space Requirements for the Boxed Processor (Top View)89Figure 7-4. Space Requirements for the Boxed Processor (Overall View)897.1.2 Boxed Processor Fan Heatsink Weight897.1.3 Boxed Processor Retention Mechanism and Heatsink Attach Clip Assembly907.2 Electrical Requirements907.2.1 Fan Heatsink Power Supply90Figure 7-5. Boxed Processor Fan Heatsink Power Cable Connector Description90Table 7-1. Fan Heatsink Power and Signal Specifications91Figure 7-6. Baseboard Power Header Placement Relative to Processor Socket917.3 Thermal Specifications917.3.1 Boxed Processor Cooling Requirements91Figure 7-7. Boxed Processor Fan Heatsink Airspace Keepout Requirements (Side 1 View)92Figure 7-8. Boxed Processor Fan Heatsink Airspace Keepout Requirements (Side 2 View)937.3.2 Fan Speed Control Operation938 Debug Tools Specifications958.1 Logic Analyzer Interface (LAI)958.1.1 Mechanical Considerations958.1.2 Electrical Considerations95Dimensioni: 1,37 MBPagine: 96Language: EnglishApri il manuale
