Manuali utente per Fujitsu Xeon 5050

Sommario

• Dual-Core Intel® Xeon® Processor 5000 Series

  1
• Contents

  3
  • Figures

    4
  • Tables

    5
• Revision History

  7
• Features

  8
• 1 Introduction

  9
  • 1.1 Terminology

    11
  • 1.2 State of Data

    12
  • 1.3 References

    12
• 2 Electrical Specifications

  15
  • 2.1 Front Side Bus and GTLREF

    15
  • 2.2 Power and Ground Lands

    15
  • 2.3 Decoupling Guidelines

    16
    • 2.3.1 VCC Decoupling

      16
    • 2.3.2 VTT Decoupling

      16
    • 2.3.3 Front Side Bus AGTL+ Decoupling

      16
  • 2.4 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking

    16
    • 2.4.1 Front Side Bus Frequency Select Signals (BSEL[2:0])

      17
    • 2.4.2 Phase Lock Loop (PLL) and Filter

      18
  • 2.5 Voltage Identification (VID)

    19
  • 2.6 Reserved or Unused Signals

    21
  • 2.7 Front Side Bus Signal Groups

    21
  • 2.8 GTL+ Asynchronous and AGTL+ Asynchronous Signals

    23
  • 2.9 Test Access Port (TAP) Connection

    23
  • 2.10 Mixing Processors

    24
  • 2.11 Absolute Maximum and Minimum Ratings

    24
  • 2.12 Processor DC Specifications

    25
    • 2.12.1 VCC Overshoot Specification

      31
    • 2.12.2 Die Voltage Validation

      32
• 3 Mechanical Specifications

  33
  • 3.1 Package Mechanical Drawings

    33
  • 3.2 Processor Component Keepout Zones

    37
  • 3.3 Package Loading Specifications

    37
  • 3.4 Package Handling Guidelines

    38
  • 3.5 Package Insertion Specifications

    38
  • 3.6 Processor Mass Specifications

    38
  • 3.7 Processor Materials

    38
  • 3.8 Processor Markings

    39
  • 3.9 Processor Land Coordinates

    40
• 4 Land Listing

  43
  • 4.1 Dual-Core Intel Xeon Processor 5000 Series Land Assignments

    43
    • 4.1.1 Land Listing by Land Name

      43
    • 4.1.2 Land Listing by Land Number

      52
• 5 Signal Definitions

  61
  • 5.1 Signal Definitions

    61
• 6 Thermal Specifications

  69
  • 6.1 Package Thermal Specifications

    69
    • 6.1.1 Thermal Specifications

      69
    • 6.1.2 Thermal Metrology

      75
  • 6.2 Processor Thermal Features

    77
    • 6.2.1 Thermal Monitor

      77
    • 6.2.2 On-Demand Mode

      77
    • 6.2.3 PROCHOT# Signal

      78
    • 6.2.4 FORCEPR# Signal

      78
    • 6.2.5 THERMTRIP# Signal

      78
    • 6.2.6 Tcontrol and Fan Speed Reduction

      79
    • 6.2.7 Thermal Diode

      79
• 7 Features

  83
  • 7.1 Power-On Configuration Options

    83
  • 7.2 Clock Control and Low Power States

    83
    • 7.2.1 Normal State

      84
    • 7.2.2 HALT or Enhanced Powerdown States

      84
    • 7.2.3 Stop-Grant State

      85
    • 7.2.4 Enhanced HALT Snoop or HALT Snoop State, Stop Grant Snoop State

      86
  • 7.3 Enhanced Intel SpeedStep® Technology

    86
• 8 Boxed Processor Specifications

  89
  • 8.1 Introduction

    89
  • 8.2 Mechanical Specifications

    90
    • 8.2.1 Boxed Processor Heat Sink Dimensions (CEK)

      91
    • 8.2.2 Boxed Processor Heat Sink Weight

      99
    • 8.2.3 Boxed Processor Retention Mechanism and Heat Sink Support (CEK)

      99
  • 8.3 Electrical Requirements

    99
    • 8.3.1 Fan Power Supply (Active CEK)

      99
    • 8.3.2 Boxed Processor Cooling Requirements

      100
  • 8.4 Boxed Processor Contents

    101
• 9 Debug Tools Specifications

  103
  • 9.1 Debug Port System Requirements

    103
  • 9.2 Target System Implementation

    103
    • 9.2.1 System Implementation

      103
  • 9.3 Logic Analyzer Interface (LAI)

    103
    • 9.3.1 Mechanical Considerations

      104
    • 9.3.2 Electrical Considerations

      104