Manuali utente per HP A2Y15AV

Sommario

• 1 Introduction

  13
• 2 Processor Configuration Registers

  15
  • 2.1 Register Terminology

    15
  • 2.2 PCI Devices and Functions

    16
  • 2.3 System Address Map

    17
    • 2.3.1 Legacy Address Range

      19
      • 2.3.1.1 DOS Range (0h–9_FFFFh)

        20
      • 2.3.1.2 Legacy Video Area (A_0000h–B_FFFFh)

        20
      • 2.3.1.3 PAM (C_0000h–F_FFFFh)

        21
    • 2.3.2 Main Memory Address Range (1 MB – TOLUD)

      22
      • 2.3.2.1 ISA Hole (15 MB – 16 MB)

        22
      • 2.3.2.2 TSEG

        23
      • 2.3.2.3 Protected Memory Range (PMR) – (programmable)

        23
      • 2.3.2.4 DRAM Protected Range (DPR)

        24
      • 2.3.2.5 Pre-allocated Memory

        24
      • 2.3.2.6 Graphics Stolen Spaces

        24
      • 2.3.2.7 Intel® Management Engine (Intel® ME) UMA

        25
    • 2.3.3 PCI Memory Address Range (TOLUD – 4 GB)

      25
      • 2.3.3.1 APIC Configuration Space (FEC0_0000h – FECF_FFFFh)

        26
      • 2.3.3.2 HSEG (FEDA_0000h – FEDB_FFFFh)

        27
      • 2.3.3.3 MSI Interrupt Memory Space (FEE0_0000 – FEEF_FFFF)

        27
      • 2.3.3.4 High BIOS Area

        27
    • 2.3.4 Main Memory Address Space (4 GB to TOUUD)

      27
      • 2.3.4.1 Memory Re-claim Background

        28
      • 2.3.4.2 Indirect Accesses to MCHBAR Registers

        29
      • 2.3.4.3 Memory Remapping

        29
      • 2.3.4.4 Hardware Remap Algorithm

        29
      • 2.3.4.5 Programming Model

        30
    • 2.3.5 PCI Express* Configuration Address Space

      35
    • 2.3.6 PCI Express* Graphics Attach (PEG)

      35
    • 2.3.7 Graphics Memory Address Ranges

      36
      • 2.3.7.1 IOBAR Mapped Access to Device 2 MMIO Space

        36
      • 2.3.7.2 Trusted Graphics Ranges

        36
    • 2.3.8 System Management Mode (SMM)

      37
    • 2.3.9 SMM and VGA Access through GTT TLB

      37
    • 2.3.10 ME Stolen Memory Accesses

      37
    • 2.3.11 I/O Address Space

      38
      • 2.3.11.1 PCI Express* I/O Address Mapping

        38
    • 2.3.12 MCTP and KVM Flows

      39
    • 2.3.13 Decode Rules and Cross-Bridge Address Mapping

      39
      • 2.3.13.1 DMI Interface Decode Rules

        39
      • 2.3.13.2 PCI Express* Interface Decode Rules

        42
      • 2.3.13.3 Legacy VGA and I/O Range Decode Rules

        43
  • 2.4 I/O Mapped Registers

    46
  • 2.5 PCI Device 0 Function 0 Configuration Space Registers

    47
    • 2.5.1 VID—Vendor Identification Register

      48
    • 2.5.2 DID—Device Identification Register

      49
    • 2.5.3 PCICMD—PCI Command Register

      49
    • 2.5.4 PCISTS—PCI Status Register

      50
    • 2.5.5 RID—Revision Identification Register

      52
    • 2.5.6 CC—Class Code Register

      52
    • 2.5.7 HDR—Header Type Register

      53
    • 2.5.8 SVID—Subsystem Vendor Identification Register

      53
    • 2.5.9 SID—Subsystem Identification Register

      53
    • 2.5.10 CAPPTR—Capabilities Pointer Register

      54
    • 2.5.11 PXPEPBAR—PCI Express* Egress Port Base Address Register

      54
    • 2.5.12 MCHBAR—Host Memory Mapped Register Range Base Register

      55
    • 2.5.13 GGC—GMCH Graphics Control Register

      55
    • 2.5.14 DEVEN—Device Enable Register

      57
    • 2.5.15 PAVPC—Protected Audio Video Path Control Register

      59
    • 2.5.16 DPR—DMA Protected Range Register

      59
    • 2.5.17 PCIEXBAR—PCI Express* Register Range Base Address Register

      60
    • 2.5.18 DMIBAR—Root Complex Register Range Base Address Register

      62
    • 2.5.19 MESEG_BASE—Intel® Management Engine Base Address Register

      63
    • 2.5.20 MESEG_MASK—Intel® Management Engine Limit Address Register

      64
    • 2.5.21 PAM0—Programmable Attribute Map 0 Register

      65
    • 2.5.22 PAM1—Programmable Attribute Map 1 Register

      66
    • 2.5.23 PAM2—Programmable Attribute Map 2 Register

      67
    • 2.5.24 PAM3—Programmable Attribute Map 3 Register

      68
    • 2.5.25 PAM4—Programmable Attribute Map 4 Register

      69
    • 2.5.26 PAM5—Programmable Attribute Map 5 Register

      70
    • 2.5.27 PAM6—Programmable Attribute Map 6 Register

      71
    • 2.5.28 LAC—Legacy Access Control Register

      72
    • 2.5.29 REMAPBASE—Remap Base Address Register

      76
    • 2.5.30 REMAPLIMIT—Remap Limit Address Register

      77
    • 2.5.31 TOM—Top of Memory Register

      77
    • 2.5.32 TOUUD—Top of Upper Usable DRAM Register

      78
    • 2.5.33 BDSM—Base Data of Stolen Memory Register

      79
    • 2.5.34 BGSM—Base of GTT Stolen Memory Register

      79
    • 2.5.35 TSEGMB—TSEG Memory Base Register

      80
    • 2.5.36 TOLUD—Top of Low Usable DRAM Register

      80
    • 2.5.37 SKPD—Scratchpad Data Register

      81
    • 2.5.38 CAPID0_A—Capabilities A Register

      82
    • 2.5.39 CAPID0_B—Capabilities B Register

      84
  • 2.6 PCI Device 1 Function 0–2 Configuration Space Registers

    86
    • 2.6.1 VID—Vendor Identification Register

      87
    • 2.6.2 DID—Device Identification Register

      88
    • 2.6.3 PCICMD—PCI Command Register

      88
    • 2.6.4 PCISTS—PCI Status Register

      90
    • 2.6.5 RID—Revision Identification Register

      92
    • 2.6.6 CC—Class Code Register

      92
    • 2.6.7 CL—Cache Line Size Register

      92
    • 2.6.8 HDR—Header Type Register

      93
    • 2.6.9 PBUSN—Primary Bus Number Register

      93
    • 2.6.10 SBUSN—Secondary Bus Number Register

      93
    • 2.6.11 SUBUSN—Subordinate Bus Number Register

      94
    • 2.6.12 IOBASE—I/O Base Address Register

      95
    • 2.6.13 IOLIMIT—I/O Limit Address Register

      95
    • 2.6.14 SSTS—Secondary Status Register

      96
    • 2.6.15 MBASE—Memory Base Address Register

      97
    • 2.6.16 MLIMIT—Memory Limit Address Register

      98
    • 2.6.17 PMBASE—Prefetchable Memory Base Address Register

      99
    • 2.6.18 PMLIMIT—Prefetchable Memory Limit Address Register

      100
    • 2.6.19 PMBASEU—Prefetchable Memory Base Address Upper Register

      100
    • 2.6.20 PMLIMITU—Prefetchable Memory Limit Address Upper Register

      101
    • 2.6.21 CAPPTR—Capabilities Pointer Register

      101
    • 2.6.22 INTRLINE—Interrupt Line Register

      102
    • 2.6.23 INTRPIN—Interrupt Pin Register

      102
    • 2.6.24 BCTRL—Bridge Control Register

      103
    • 2.6.25 PM_CAPID—Power Management Capabilities Register

      104
    • 2.6.26 PM_CS—Power Management Control/Status Register

      105
    • 2.6.27 SS_CAPID—Subsystem ID and Vendor ID Capabilities Register

      107
    • 2.6.28 SS—Subsystem ID and Subsystem Vendor ID Register

      107
    • 2.6.29 MSI_CAPID—Message Signaled Interrupts Capability ID Register

      108
    • 2.6.30 MC—Message Control Register

      109
    • 2.6.31 MA—Message Address Register

      110
    • 2.6.32 MD—Message Data Register

      110
    • 2.6.33 PEG_CAPL—PCI Express-G Capability List Register

      110
    • 2.6.34 PEG_CAP—PCI Express-G Capabilities Register

      111
    • 2.6.35 DCAP—Device Capabilities Register

      111
    • 2.6.36 DCTL—Device Control Register

      112
    • 2.6.37 DSTS—Device Status Register

      113
    • 2.6.38 LCAP—Link Capabilities Register

      114
    • 2.6.39 LCTL—Link Control Register

      116
    • 2.6.40 LSTS—Link Status Register

      118
    • 2.6.41 SLOTCAP—Slot Capabilities Register

      119
    • 2.6.42 SLOTCTL—Slot Control Register

      121
    • 2.6.43 SLOTSTS—Slot Status Register

      123
    • 2.6.44 RCTL—Root Control Register

      125
    • 2.6.45 RSTS—Root Status Register

      126
    • 2.6.46 DCAP2—Device Capabilities 2 Register

      127
    • 2.6.47 DCTL2—Device Control 2 Register

      128
    • 2.6.48 LCAP2—Link Capabilities 2 Register

      129
    • 2.6.49 LCTL2—Link Control 2 Register

      129
    • 2.6.50 LSTS2—Link Status 2 Register

      131
  • 2.7 PCI Device 1 Function 0–2 Extended Configuration Registers

    132
    • 2.7.1 PVCCAP1—Port VC Capability Register 1

      133
    • 2.7.2 PVCCAP2—Port VC Capability Register 2

      133
    • 2.7.3 PVCCTL—Port VC Control Register

      134
    • 2.7.4 VC0RCAP—VC0 Resource Capability Register

      135
    • 2.7.5 VC0RCTL—VC0 Resource Control Register

      136
    • 2.7.6 VC0RSTS—VC0 Resource Status Register

      137
    • 2.7.7 PEG_TC—PCI Express* Completion Timeout Register

      137
    • 2.7.8 EQCTL0_1—Lane 0/1 Equalization Control Register

      138
    • 2.7.9 EQCTL2_3—Lane 2/3 Equalization Control Register

      139
    • 2.7.10 EQCTL4_5—Lane 4/5 Equalization Control Register

      140
    • 2.7.11 EQCTL6_7—Lane 6/7 Equalization Control Register

      141
    • 2.7.12 EQCTL8_9—Lane 8/9 Equalization Control Register

      142
    • 2.7.13 EQCTL10_11—Lane 10/11 Equalization Control Register

      143
    • 2.7.14 EQCTL12_13—Lane 12/13 Equalization Control Register

      144
    • 2.7.15 EQCTL14_15—Lane 14/15 Equalization Control Register

      145
    • 2.7.16 EQCFG—Equalization Configuration Register

      146
  • 2.8 PCI Device 2 Configuration Space Registers

    148
    • 2.8.1 VID2—Vendor Identification Register

      149
    • 2.8.2 DID2—Device Identification Register

      149
    • 2.8.3 PCICMD2—PCI Command Register

      150
    • 2.8.4 PCISTS2—PCI Status Register

      151
    • 2.8.5 RID2—Revision Identification Register

      152
    • 2.8.6 CC—Class Code Register

      152
    • 2.8.7 CLS—Cache Line Size Register

      153
    • 2.8.8 MLT2—Master Latency Timer Register

      153
    • 2.8.9 HDR2—Header Type Register

      153
    • 2.8.10 GTTMMADR—Graphics Translation Table, Memory Mapped Range Address Register

      154
    • 2.8.11 GMADR—Graphics Memory Range Address Register

      155
    • 2.8.12 IOBAR—I/O Base Address Register

      156
    • 2.8.13 SVID2—Subsystem Vendor Identification Register

      156
    • 2.8.14 SID2—Subsystem Identification Register

      157
    • 2.8.15 ROMADR—Video BIOS ROM Base Address Register

      157
    • 2.8.16 CAPPOINT—Capabilities Pointer Register

      157
    • 2.8.17 INTRLINE—Interrupt Line Register

      158
    • 2.8.18 INTRPIN—Interrupt Pin Register

      158
    • 2.8.19 MINGNT—Minimum Grant Register

      158
    • 2.8.20 MAXLAT—Maximum Latency Register

      159
    • 2.8.21 MSAC—Multi Size Aperture Control Register

      159
  • 2.9 Device 2 IO Registers

    160
    • 2.9.1 Index—MMIO Address Register

      160
    • 2.9.2 Data—MMIO Data Register

      160
  • 2.10 PCI Device 6 Registers

    161
    • 2.10.1 VID—Vendor Identification Register

      162
    • 2.10.2 DID—Device Identification Register

      163
    • 2.10.3 PCICMD—PCI Command Register

      163
    • 2.10.4 PCISTS—PCI Status Register

      166
    • 2.10.5 RID—Revision Identification Register

      167
    • 2.10.6 CC—Class Code Register

      168
    • 2.10.7 CL—Cache Line Size Register

      168
    • 2.10.8 HDR—Header Type Register

      168
    • 2.10.9 PBUSN—Primary Bus Number Register

      169
    • 2.10.10 SBUSN—Secondary Bus Number Register

      169
    • 2.10.11 SUBUSN—Subordinate Bus Number Register

      169
    • 2.10.12 IOBASE—I/O Base Address Register

      170
    • 2.10.13 IOLIMIT—I/O Limit Address Register

      170
    • 2.10.14 SSTS—Secondary Status Register

      171
    • 2.10.15 MBASE—Memory Base Address Register

      172
    • 2.10.16 MLIMIT—Memory Limit Address Register

      173
    • 2.10.17 PMBASE—Prefetchable Memory Base Address Register

      174
    • 2.10.18 PMLIMIT—Prefetchable Memory Limit Address Register

      175
    • 2.10.19 PMBASEU—Prefetchable Memory Base Address Upper Register

      176
    • 2.10.20 PMLIMITU—Prefetchable Memory Limit Address Upper Register

      177
    • 2.10.21 CAPPTR—Capabilities Pointer Register

      178
    • 2.10.22 INTRLINE—Interrupt Line Register

      178
    • 2.10.23 INTRPIN—Interrupt Pin Register

      179
    • 2.10.24 BCTRL—Bridge Control Register

      179
    • 2.10.25 PM_CAPID—Power Management Capabilities Register

      181
    • 2.10.26 PM_CS—Power Management Control/Status Register

      182
    • 2.10.27 SS_CAPID—Subsystem ID and Vendor ID Capabilities Register

      184
    • 2.10.28 SS—Subsystem ID and Subsystem Vendor ID Register

      184
    • 2.10.29 MSI_CAPID—Message Signaled Interrupts Capability ID Register

      185
    • 2.10.30 MC—Message Control Register

      185
    • 2.10.31 MA—Message Address Register

      186
    • 2.10.32 MD—Message Data Register

      187
    • 2.10.33 PEG_CAPL—PCI Express-G Capability List Register

      187
    • 2.10.34 PEG_CAP—PCI Express-G Capabilities Register

      188
    • 2.10.35 DCAP—Device Capabilities Register

      188
    • 2.10.36 DCTL—Device Control Register

      189
    • 2.10.37 DSTS—Device Status Register

      190
    • 2.10.38 LCAP—Link Capabilities Register

      191
    • 2.10.39 LCTL—Link Control Register

      193
    • 2.10.40 LSTS—Link Status Register

      195
    • 2.10.41 SLOTCAP—Slot Capabilities Register

      196
    • 2.10.42 SLOTCTL—Slot Control Register

      198
    • 2.10.43 SLOTSTS—Slot Status Register

      200
    • 2.10.44 RCTL—Root Control Register

      202
    • 2.10.45 LCAP2—Link Capabilities 2 Register

      202
  • 2.11 PCI Device 6 Extended Configuration Registers

    203
    • 2.11.1 PVCCAP1—Port VC Capability Register 1

      204
    • 2.11.2 PVCCAP2—Port VC Capability Register 2

      204
    • 2.11.3 PVCCTL—Port VC Control Register

      205
    • 2.11.4 VC0RCAP—VC0 Resource Capability Register

      205
    • 2.11.5 VC0RCTL—VC0 Resource Control Register

      207
    • 2.11.6 VC0RSTS—VC0 Resource Status Register

      208
    • 2.11.7 RCLDECH—Root Complex Link Declaration Enhanced

      208
    • 2.11.8 ESD—Element Self Description Register

      209
    • 2.11.9 LE1D—Link Entry 1 Description Register

      210
    • 2.11.10 LE1A—Link Entry 1 Address Register

      210
    • 2.11.11 LE1AH—Link Entry 1 Address Register

      211
    • 2.11.12 APICBASE—APIC Base Address Register

      211
    • 2.11.13 APICLIMIT—APIC Base Address Limit Register

      212
    • 2.11.14 CMNRXERR—Common Rx Error Register

      212
    • 2.11.15 PEGTST—PCI Express* Test Modes Register

      213
    • 2.11.16 PEGUPDNCFG—PEG UPconfig/DNconfig Control Register

      213
    • 2.11.17 BGFCTL3—BGF Control 3 Register

      214
    • 2.11.18 EQPRESET1_2—Equalization Preset 1/2 Register

      215
    • 2.11.19 EQPRESET2_3_4—Equalization Preset 2/3/4 Register

      215
    • 2.11.20 EQPRESET6_7—Equalization Preset 6/7 Register

      216
    • 2.11.21 EQCFG—Equalization Configuration Register

      216
  • 2.12 Direct Media Interface Base Address Registers (DMIBAR)

    217
    • 2.12.1 DMIVCECH—DMI Virtual Channel Enhanced Capability Register

      218
    • 2.12.2 DMIPVCCAP1—DMI Port VC Capability Register 1

      219
    • 2.12.3 DMIPVCCAP2—DMI Port VC Capability Register 2

      219
    • 2.12.4 DMIPVCCTL—DMI Port VC Control Register

      220
    • 2.12.5 DMIVC0RCAP—DMI VC0 Resource Capability Register

      220
    • 2.12.6 DMIVC0RCTL—DMI VC0 Resource Control Register

      221
    • 2.12.7 DMIVC0RSTS—DMI VC0 Resource Status Register

      222
    • 2.12.8 DMIVC1RCAP—DMI VC1 Resource Capability Register

      222
    • 2.12.9 DMIVC1RCTL—DMI VC1 Resource Control Register

      223
    • 2.12.10 DMIVC1RSTS—DMI VC1 Resource Status Register

      224
    • 2.12.11 DMIVCPRCAP—DMI VCp Resource Capability Register

      224
    • 2.12.12 DMIVCPRCTL—DMI VCp Resource Control Register

      225
    • 2.12.13 DMIVCPRSTS—DMI VCp Resource Status Register

      226
    • 2.12.14 DMIVCMRCAP—DMI VCm Resource Capability Register

      226
    • 2.12.15 DMIVCMRCTL—DMI VCm Resource Control Register

      227
    • 2.12.16 DMIVCMRSTS—DMI VCm Resource Status Register

      228
    • 2.12.17 DMIRCLDECH—DMI Root Complex Link Declaration Register

      228
    • 2.12.18 DMIESD—DMI Element Self Description Register

      229
    • 2.12.19 DMILE1D—DMI Link Entry 1 Description Register

      230
    • 2.12.20 DMILE1A—DMI Link Entry 1 Address Register

      231
    • 2.12.21 DMILUE1A—DMI Link Upper Entry 1 Address Register

      231
    • 2.12.22 DMILE2D—DMI Link Entry 2 Description Register

      232
    • 2.12.23 DMILE2A—DMI Link Entry 2 Address Register

      233
    • 2.12.24 LCAP—Link Capabilities Register

      233
    • 2.12.25 LCTL—Link Control Register

      234
    • 2.12.26 LSTS—DMI Link Status Register

      235
    • 2.12.27 LCTL2—Link Control 2 Register

      236
    • 2.12.28 LSTS2—Link Status 2 Register

      238
  • 2.13 MCHBAR Registers in Memory Controller—Channel 0 Registers

    239
    • 2.13.1 TC_DBP_C0—Timing of DDR – Bin Parameters Register

      240
    • 2.13.2 TC_RAP_C0—Timing of DDR – Regular Access Parameters Register

      241
    • 2.13.3 SC_IO_LATENCY_C0—IO Latency configuration Register

      242
    • 2.13.4 TC_SRFTP_C0–Self Refresh Timing Parameters Register

      242
    • 2.13.5 PM_PDWN_config_C0–Power-down Configuration Register

      243
    • 2.13.6 TC_RFP_C0—Refresh Parameters Register

      244
    • 2.13.7 TC_RFTP_C0—Refresh Timing Parameters Register

      244
  • 2.14 MCHBAR Registers in Memory Controller – Channel 1

    245
    • 2.14.1 TC_DBP_C1—Timing of DDR – Bin Parameters Register

      245
    • 2.14.2 TC_RAP_C1—Timing of DDR – Regular Access Parameters Register

      246
    • 2.14.3 SC_IO_LATENCY_C1—IO Latency configuration Register

      247
    • 2.14.4 PM_PDWN_config_C1—Power-down Configuration Register

      248
    • 2.14.5 TC_RFP_C1—Refresh Parameters Register

      249
    • 2.14.6 TC_RFTP_C1—Refresh Timing Parameters Register

      250
    • 2.14.7 TC_SRFTP_C1—Self refresh Timing Parameters Register

      250
  • 2.15 MCHBAR Registers in Memory Controller – Integrated Memory Peripheral Hub (IMPH)

    251
    • 2.15.1 CRDTCTL3—Credit Control 3 Register

      251
    • 2.15.2 CRDTCTL4—Credit Control 4 Register

      252
  • 2.16 MCHBAR Registers in Memory Controller – Common

    253
    • 2.16.1 MAD_CHNL—Address Decoder Channel Configuration Register

      253
    • 2.16.2 MAD_DIMM_ch0—Address Decode Channel 0 Register

      254
    • 2.16.3 MAD_DIMM_ch1—Address Decode Channel 1 Register

      255
    • 2.16.4 PM_SREF_config—Self Refresh Configuration Register

      256
  • 2.17 Memory Controller MMIO Registers Broadcast Group Registers

    257
    • 2.17.1 PM_PDWN_config—Power-down Configuration Register

      258
    • 2.17.2 PM_CMD_PWR—Power Management Command Power Register

      259
    • 2.17.3 PM_BW_LIMIT_CONFIG—BW Limit Configuration Register

      259
  • 2.18 Integrated Graphics VTd Remapping Engine Registers

    260
    • 2.18.1 VER_REG—Version Register

      261
    • 2.18.2 CAP_REG—Capability Register

      262
    • 2.18.3 ECAP_REG—Extended Capability Register

      266
    • 2.18.4 GCMD_REG—Global Command Register

      267
    • 2.18.5 GSTS_REG—Global Status Register

      271
    • 2.18.6 RTADDR_REG—Root-Entry Table Address Register

      272
    • 2.18.7 CCMD_REG—Context Command Register

      273
    • 2.18.8 FSTS_REG—Fault Status Register

      275
    • 2.18.9 FECTL_REG—Fault Event Control Register

      277
    • 2.18.10 FEDATA_REG—Fault Event Data Register

      278
    • 2.18.11 FEADDR_REG—Fault Event Address Register

      278
    • 2.18.12 FEUADDR_REG—Fault Event Upper Address Register

      278
    • 2.18.13 AFLOG_REG—Advanced Fault Log Register

      279
    • 2.18.14 PMEN_REG—Protected Memory Enable Register

      280
    • 2.18.15 PLMBASE_REG—Protected Low-Memory Base Register

      281
    • 2.18.16 PLMLIMIT_REG—Protected Low-Memory Limit Register

      282
    • 2.18.17 PHMBASE_REG—Protected High-Memory Base Register

      283
    • 2.18.18 PHMLIMIT_REG—Protected High-Memory Limit Register

      284
    • 2.18.19 IQH_REG—Invalidation Queue Head Register

      285
    • 2.18.20 IQT_REG—Invalidation Queue Tail Register

      285
    • 2.18.21 IQA_REG—Invalidation Queue Address Register

      286
    • 2.18.22 ICS_REG—Invalidation Completion Status Register

      286
    • 2.18.23 IECTL_REG—Invalidation Event Control Register

      287
    • 2.18.24 IEDATA_REG—Invalidation Event Data Register

      288
    • 2.18.25 IEADDR_REG—Invalidation Event Address Register

      288
    • 2.18.26 IEUADDR_REG—Invalidation Event Upper Address Register

      289
    • 2.18.27 IRTA_REG—Interrupt Remapping Table Address Register

      289
    • 2.18.28 IVA_REG—Invalidate Address Register

      290
    • 2.18.29 IOTLB_REG—IOTLB Invalidate Register

      291
    • 2.18.30 FRCDL_REG—Fault Recording Low Register

      293
    • 2.18.31 FRCDH_REG—Fault Recording High Register

      294
    • 2.18.32 VTPOLICY—DMA Remap Engine Policy Control Register

      295
  • 2.19 PCU MCHBAR Registers

    296
    • 2.19.1 MEM_TRML_ESTIMATION_CONFIG—Memory Thermal Estimation Configuration Register

      297
    • 2.19.2 MEM_TRML_THRESHOLDS_CONFIG—Memory Thermal Thresholds Configuration Register

      298
    • 2.19.3 MEM_TRML_STATUS_REPORT—Memory Thermal Status Report Register

      299
    • 2.19.4 MEM_TRML_TEMPERATURE_REPORT—Memory Thermal Temperature Report Register

      300
    • 2.19.5 MEM_TRML_INTERRUPT—Memory Thermal Interrupt Register

      300
    • 2.19.6 GT_PERF_STATUS—GT Performance Status Register

      301
    • 2.19.7 RP_STATE_LIMITS—RP-State Limitations Register

      301
    • 2.19.8 RP_STATE_CAP—RP State Capability Register

      302
    • 2.19.9 PCU_MMIO_FREQ_CLIPPING_CAUSE_STATUS Register

      302
    • 2.19.10 PCU_MMIO_FREQ_CLIPPING_CAUSE_LOG Register

      304
    • 2.19.11 SSKPD—Sticky Scratchpad Data Register

      306
  • 2.20 PXPEPBAR Registers

    308
    • 2.20.1 EPVC0RCTL—EP VC 0 Resource Control Register

      308
  • 2.21 Default PEG/DMI VTd Remapping Engine Registers

    309
    • 2.21.1 VER_REG—Version Register

      310
    • 2.21.2 CAP_REG—Capability Register

      311
    • 2.21.3 ECAP_REG—Extended Capability Register

      315
    • 2.21.4 GCMD_REG—Global Command Register

      316
    • 2.21.5 GSTS_REG—Global Status Register

      320
    • 2.21.6 RTADDR_REG—Root-Entry Table Address Register

      321
    • 2.21.7 CCMD_REG—Context Command Register

      322
    • 2.21.8 FSTS_REG—Fault Status Register

      324
    • 2.21.9 FECTL_REG—Fault Event Control Register

      326
    • 2.21.10 FEDATA_REG—Fault Event Data Register

      327
    • 2.21.11 FEADDR_REG—Fault Event Address Register

      327
    • 2.21.12 FEUADDR_REG—Fault Event Upper Address Register

      327
    • 2.21.13 AFLOG_REG—Advanced Fault Log Register

      328
    • 2.21.14 PMEN_REG—Protected Memory Enable Register

      329
    • 2.21.15 PLMBASE_REG—Protected Low-Memory Base Register

      330
    • 2.21.16 PLMLIMIT_REG—Protected Low-Memory Limit Register

      331
    • 2.21.17 PHMBASE_REG—Protected High-Memory Base Register

      332
    • 2.21.18 PHMLIMIT_REG—Protected High-Memory Limit Register

      333
    • 2.21.19 IQH_REG—Invalidation Queue Head Register

      334
    • 2.21.20 IQT_REG—Invalidation Queue Tail Register

      334
    • 2.21.21 IQA_REG—Invalidation Queue Address Register

      335
    • 2.21.22 ICS_REG—Invalidation Completion Status Register

      336
    • 2.21.23 IECTL_REG—Invalidation Event Control Register

      336
    • 2.21.24 IEDATA_REG—Invalidation Event Data Register

      337
    • 2.21.25 IEADDR_REG—Invalidation Event Address Register

      338
    • 2.21.26 IEUADDR_REG—Invalidation Event Upper Address Register

      338
    • 2.21.27 IRTA_REG—Interrupt Remapping Table Address Register

      339
    • 2.21.28 IVA_REG—Invalidate Address Register

      340
    • 2.21.29 IOTLB_REG—IOTLB Invalidate Register

      341