Manuale UtenteSommarioCOVER1PREFACE7CHAPTER 1 OUTLINE241.1 Features241.2 Applications251.3 Ordering Information251.4 Quality Grade261.5 Pin Configuration (Top View)271.6 78K/0 Series Development321.7 Block Diagram341.8 Outline of Function351.9 Differences between the uPD78081, 78082 and 78P083, the uPD78081(A), 78082(A) and 78P083(A), and the uPD78081(A2)36CHAPTER 2 PIN FUNCTION382.1 Pin Function List382.1.1 Normal operating mode pins382.1.2 PROM programming mode pins ( uPD78P083 only)392.2 Description of Pin Functions402.2.1 P00 to P03 (Port 0)402.2.2 P10 to P17 (Port 1)402.2.3 P30 to P37 (Port 3)412.2.4 P50 to P57 (Port 5)412.2.5 P70 to P72 (Port 7)422.2.6 P100 to P101 (Port 10)422.2.7 AVREF432.2.8 AVDD432.2.9 AVSS432.2.10 RESET#432.2.11 X1 and X2432.2.12 VDD432.2.13 VSS432.2.14 VPP ( uPD78P083 only)432.2.15 IC (Mask ROM version only)442.2.16 NC (44-pin plastic QFP versions only)442.3 Pin Input/Output Circuits and Recommended Connection of Unused Pins45CHAPTER 3 CPU ARCHITECTURE483.1 Memory Spaces483.1.1 Internal program memory space513.1.2 Internal data memory space523.1.3 Special Function Register (SFR) area523.1.4 Data memory addressing523.2 Processor Registers563.2.1 Control registers563.2.2 General registers593.2.3 Special Function Register (SFR)603.3 Instruction Address Addressing633.3.1 Relative addressing633.3.2 Immediate addressing643.3.3 Table indirect addressing653.3.4 Register addressing663.4 Operand Address Addressing673.4.1 Implied addressing673.4.2 Register addressing683.4.3 Direct addressing693.4.4 Short direct addressing703.4.5 Special-Function Register (SFR) addressing723.4.6 Register indirect addressing733.4.7 Based addressing743.4.8 Based indexed addressing753.4.9 Stack addressing75CHAPTER 4 PORT FUNCTIONS764.1 Port Functions764.2 Port Configuration784.2.1 Port 0784.2.2 Port 1804.2.3 Port 3814.2.4 Port 5824.2.5 Port 7834.2.6 Port 10854.3 Port Function Control Registers864.4 Port Function Operations904.4.1 Writing to input/output port904.4.2 Reading from input/output port904.4.3 Operations on input/output port90CHAPTER 5 CLOCK GENERATOR925.1 Clock Generator Functions925.2 Clock Generator Configuration925.3 Clock Generator Control Register945.4 System Clock Oscillator965.4.1 Main system clock oscillator965.4.2 Scaler985.5 Clock Generator Operations995.6 Changing CPU Clock Settings1005.6.1 Time required for CPU clock switchover1005.6.2 CPU clock switching procedure101CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 61026.1 8-Bit Timer/Event Counters 5 and 6 Functions1036.2 8-Bit Timer/Event Counters 5 and 6 Configurations1056.3 8-Bit Timer/Event Counters 5 and 6 Control Registers1076.4 8-Bit Timer/Event Counters 5 and 6 Operations1136.4.1 Interval timer operations1136.4.2 External event counter operation1166.4.3 Square-wave output1176.4.4 PWM output operations1196.5 Cautions on 8-Bit Timer/Event Counters 5 and 6123CHAPTER 7 WATCHDOG TIMER1267.1 Watchdog Timer Functions1267.2 Watchdog Timer Configuration1287.3 Watchdog Timer Control Registers1297.4 Watchdog Timer Operations1327.4.1 Watchdog timer operation1327.4.2 Interval timer operation133CHAPTER 8 CLOCK OUTPUT CONTROL CIRCUIT1348.1 Clock Output Control Circuit Functions1348.2 Clock Output Control Circuit Configuration1358.3 Clock Output Function Control Registers136CHAPTER 9 BUZZER OUTPUT CONTROL CIRCUIT1389.1 Buzzer Output Control Circuit Functions1389.2 Buzzer Output Control Circuit Configuration1389.3 Buzzer Output Function Control Registers139CHAPTER 10 A/D CONVERTER14210.1 A/D Converter Functions14210.2 A/D Converter Configuration14210.3 A/D Converter Control Registers14510.4 A/D Converter Operations14910.4.1 Basic operations of A/D converter14910.4.2 Input voltage and conversion results15110.4.3 A/D converter operating mode15210.5 A/D Converter Cautions154CHAPTER 11 SERIAL INTERFACE CHANNEL 215811.1 Serial Interface Channel 2 Functions15811.2 Serial Interface Channel 2 Configuration15911.3 Serial Interface Channel 2 Control Registers16311.4 Serial Interface Channel 2 Operation17111.4.1 Operation stop mode17111.4.2 Asynchronous serial interface (UART) mode17311.4.3 3-wire serial I/O mode186CHAPTER 12 INTERRUPT FUNCTION19412.1 Interrupt Function Types19412.2 Interrupt Sources and Configuration19512.3 Interrupt Function Control Registers19812.4 Interrupt Servicing Operations20412.4.1 Non-maskable interrupt request acknowledge operation20412.4.2 Maskable interrupt request acknowledge operation20712.4.3 Software interrupt request acknowledge operation21012.4.4 Multiple interrupt servicing21012.4.5 Interrupt request reserve214CHAPTER 13 STANDBY FUNCTION21613.1 Standby Function and Configuration21613.1.1 Standby function21613.1.2 Standby function control register21713.2 Standby Function Operations21813.2.1 HALT mode21813.2.2 STOP mode221CHAPTER 14 RESET FUNCTION22414.1 Reset Function224CHAPTER 15 uPD78P08322815.1 Memory Size Switching Register22915.2 PROM Programming23015.2.1 Operating modes23015.2.2 PROM write procedure23215.2.3 PROM reading procedure23615.3 Erasure Procedure ( uPD78P083DU Only)23715.4 Opaque Film Masking the Window ( uPD78P083DU Only)23715.5 Screening of One-Time PROM Versions237CHAPTER 16 INSTRUCTION23816.1 Legends Used in Operation List23916.1.1 Operand identifiers and description methods23916.1.2 Description of “operation” column24016.1.3 Description of “flag operation” column24016.2 Operation List24116.3 Instructions Listed by Addressing Type249APPENDIX A DEVELOPMENT TOOLS254A.1 Language Processing Software256A.2 PROM Programming Tools257A.2.1 Hardware257A.2.2 Software257A.3 Debugging Tools258A.3.1 Hardware258A.3.2 Software (1/3)259A.3.2 Software (2/3)260A.3.2 Software (3/3)261A.4 OS for IBM PC262A.5 System-Upgrade Method from Other In-Circuit Emulators to 78K/0 Series In-Circuit Emulator263APPENDIX B EMBEDDED SOFTWARE266B.1 Real-time OS267B.2 Fuzzy Inference Development Support System268APPENDIX C REGISTER INDEX270C.1 Register Index270APPENDIX D REVISION HISTORY272Dimensioni: 1,35 MBPagine: 274Language: EnglishApri il manuale
Manuale UtenteSommarioCOVER1PREFACE7CHAPTER 1 OUTLINE241.1 Features241.2 Applications251.3 Ordering Information251.4 Quality Grade261.5 Pin Configuration (Top View)271.6 78K/0 Series Development321.7 Block Diagram341.8 Outline of Function351.9 Differences between the uPD78081, 78082 and 78P083, the uPD78081(A), 78082(A) and 78P083(A), and the uPD78081(A2)36CHAPTER 2 PIN FUNCTION382.1 Pin Function List382.1.1 Normal operating mode pins382.1.2 PROM programming mode pins ( uPD78P083 only)392.2 Description of Pin Functions402.2.1 P00 to P03 (Port 0)402.2.2 P10 to P17 (Port 1)402.2.3 P30 to P37 (Port 3)412.2.4 P50 to P57 (Port 5)412.2.5 P70 to P72 (Port 7)422.2.6 P100 to P101 (Port 10)422.2.7 AVREF432.2.8 AVDD432.2.9 AVSS432.2.10 RESET#432.2.11 X1 and X2432.2.12 VDD432.2.13 VSS432.2.14 VPP ( uPD78P083 only)432.2.15 IC (Mask ROM version only)442.2.16 NC (44-pin plastic QFP versions only)442.3 Pin Input/Output Circuits and Recommended Connection of Unused Pins45CHAPTER 3 CPU ARCHITECTURE483.1 Memory Spaces483.1.1 Internal program memory space513.1.2 Internal data memory space523.1.3 Special Function Register (SFR) area523.1.4 Data memory addressing523.2 Processor Registers563.2.1 Control registers563.2.2 General registers593.2.3 Special Function Register (SFR)603.3 Instruction Address Addressing633.3.1 Relative addressing633.3.2 Immediate addressing643.3.3 Table indirect addressing653.3.4 Register addressing663.4 Operand Address Addressing673.4.1 Implied addressing673.4.2 Register addressing683.4.3 Direct addressing693.4.4 Short direct addressing703.4.5 Special-Function Register (SFR) addressing723.4.6 Register indirect addressing733.4.7 Based addressing743.4.8 Based indexed addressing753.4.9 Stack addressing75CHAPTER 4 PORT FUNCTIONS764.1 Port Functions764.2 Port Configuration784.2.1 Port 0784.2.2 Port 1804.2.3 Port 3814.2.4 Port 5824.2.5 Port 7834.2.6 Port 10854.3 Port Function Control Registers864.4 Port Function Operations904.4.1 Writing to input/output port904.4.2 Reading from input/output port904.4.3 Operations on input/output port90CHAPTER 5 CLOCK GENERATOR925.1 Clock Generator Functions925.2 Clock Generator Configuration925.3 Clock Generator Control Register945.4 System Clock Oscillator965.4.1 Main system clock oscillator965.4.2 Scaler985.5 Clock Generator Operations995.6 Changing CPU Clock Settings1005.6.1 Time required for CPU clock switchover1005.6.2 CPU clock switching procedure101CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 61026.1 8-Bit Timer/Event Counters 5 and 6 Functions1036.2 8-Bit Timer/Event Counters 5 and 6 Configurations1056.3 8-Bit Timer/Event Counters 5 and 6 Control Registers1076.4 8-Bit Timer/Event Counters 5 and 6 Operations1136.4.1 Interval timer operations1136.4.2 External event counter operation1166.4.3 Square-wave output1176.4.4 PWM output operations1196.5 Cautions on 8-Bit Timer/Event Counters 5 and 6123CHAPTER 7 WATCHDOG TIMER1267.1 Watchdog Timer Functions1267.2 Watchdog Timer Configuration1287.3 Watchdog Timer Control Registers1297.4 Watchdog Timer Operations1327.4.1 Watchdog timer operation1327.4.2 Interval timer operation133CHAPTER 8 CLOCK OUTPUT CONTROL CIRCUIT1348.1 Clock Output Control Circuit Functions1348.2 Clock Output Control Circuit Configuration1358.3 Clock Output Function Control Registers136CHAPTER 9 BUZZER OUTPUT CONTROL CIRCUIT1389.1 Buzzer Output Control Circuit Functions1389.2 Buzzer Output Control Circuit Configuration1389.3 Buzzer Output Function Control Registers139CHAPTER 10 A/D CONVERTER14210.1 A/D Converter Functions14210.2 A/D Converter Configuration14210.3 A/D Converter Control Registers14510.4 A/D Converter Operations14910.4.1 Basic operations of A/D converter14910.4.2 Input voltage and conversion results15110.4.3 A/D converter operating mode15210.5 A/D Converter Cautions154CHAPTER 11 SERIAL INTERFACE CHANNEL 215811.1 Serial Interface Channel 2 Functions15811.2 Serial Interface Channel 2 Configuration15911.3 Serial Interface Channel 2 Control Registers16311.4 Serial Interface Channel 2 Operation17111.4.1 Operation stop mode17111.4.2 Asynchronous serial interface (UART) mode17311.4.3 3-wire serial I/O mode186CHAPTER 12 INTERRUPT FUNCTION19412.1 Interrupt Function Types19412.2 Interrupt Sources and Configuration19512.3 Interrupt Function Control Registers19812.4 Interrupt Servicing Operations20412.4.1 Non-maskable interrupt request acknowledge operation20412.4.2 Maskable interrupt request acknowledge operation20712.4.3 Software interrupt request acknowledge operation21012.4.4 Multiple interrupt servicing21012.4.5 Interrupt request reserve214CHAPTER 13 STANDBY FUNCTION21613.1 Standby Function and Configuration21613.1.1 Standby function21613.1.2 Standby function control register21713.2 Standby Function Operations21813.2.1 HALT mode21813.2.2 STOP mode221CHAPTER 14 RESET FUNCTION22414.1 Reset Function224CHAPTER 15 uPD78P08322815.1 Memory Size Switching Register22915.2 PROM Programming23015.2.1 Operating modes23015.2.2 PROM write procedure23215.2.3 PROM reading procedure23615.3 Erasure Procedure ( uPD78P083DU Only)23715.4 Opaque Film Masking the Window ( uPD78P083DU Only)23715.5 Screening of One-Time PROM Versions237CHAPTER 16 INSTRUCTION23816.1 Legends Used in Operation List23916.1.1 Operand identifiers and description methods23916.1.2 Description of “operation” column24016.1.3 Description of “flag operation” column24016.2 Operation List24116.3 Instructions Listed by Addressing Type249APPENDIX A DEVELOPMENT TOOLS254A.1 Language Processing Software256A.2 PROM Programming Tools257A.2.1 Hardware257A.2.2 Software257A.3 Debugging Tools258A.3.1 Hardware258A.3.2 Software (1/3)259A.3.2 Software (2/3)260A.3.2 Software (3/3)261A.4 OS for IBM PC262A.5 System-Upgrade Method from Other In-Circuit Emulators to 78K/0 Series In-Circuit Emulator263APPENDIX B EMBEDDED SOFTWARE266B.1 Real-time OS267B.2 Fuzzy Inference Development Support System268APPENDIX C REGISTER INDEX270C.1 Register Index270APPENDIX D REVISION HISTORY272Dimensioni: 1,35 MBPagine: 274Language: EnglishApri il manuale
