Manuale Utente (SLA9X)SommarioContents3Figures5Tables6Revision History7Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Series Features91 Introduction111.1 Terminology121.1.1 Processor Terminology121.2 References14Table 1. Reference Documents142 Electrical Specifications152.1 Power and Ground Lands152.2 Decoupling Guidelines152.2.1 VCC Decoupling152.2.2 Vtt Decoupling152.2.3 FSB Decoupling162.3 Voltage Identification16Table 2. Voltage Identification Definition172.4 Market Segment Identification (MSID)18Table 3. Market Segment Selection Truth Table for MSID[1:0], , ,182.5 Reserved, Unused, and TESTHI Signals182.6 Voltage and Current Specification192.6.1 Absolute Maximum and Minimum Ratings19Table 4. Absolute Maximum and Minimum Ratings202.6.2 DC Voltage and Current Specification20Table 5. Voltage and Current Specifications20Table 6. VCC Static and Transient Tolerance22Figure 1. VCC Static and Transient Tolerance232.6.3 VCC Overshoot24Table 7. VCC Overshoot Specifications24Figure 2. VCC Overshoot Example Waveform242.6.4 Die Voltage Validation242.7 Signaling Specifications252.7.1 FSB Signal Groups25Table 8. FSB Signal Groups (Sheet 1 of 2)25Table 9. Signal Characteristics26Table 10. Signal Reference Voltages262.7.2 CMOS and Open Drain Signals272.7.3 Processor DC Specifications27Table 11. GTL+ Signal Group DC Specifications27Table 12. Open Drain and TAP Output Signal Group DC Specifications27Table 13. CMOS Signal Group DC Specifications282.7.3.1 GTL+ Front Side Bus Specifications28Table 14. GTL+ Bus Voltage Definitions282.7.4 Clock Specifications292.7.5 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking29Table 15. Core Frequency to FSB Multiplier Configuration292.7.6 FSB Frequency Select Signals (BSEL[2:0])29Table 16. BSEL[2:0] Frequency Table for BCLK[1:0]302.7.7 Phase Lock Loop (PLL) and Filter302.7.8 BCLK[1:0] Specifications (CK505 based Platforms)30Table 17. Front Side Bus Differential BCLK Specifications30Figure 3. Differential Clock Waveform31Figure 4. Differential Clock Crosspoint Specification31Figure 5. Differential Measurements312.7.9 BCLK[1:0] Specifications (CK410 based Platforms)32Table 18. Front Side Bus Differential BCLK Specifications32Figure 6. Differential Clock Crosspoint Specification322.8 PECI DC Specifications33Table 19. PECI DC Electrical Limits333 Package Mechanical Specifications35Figure 7. Processor Package Assembly Sketch353.1 Package Mechanical Drawing35Figure 8. Processor Package Drawing Sheet 1 of 336Figure 9. Processor Package Drawing Sheet 2 of 337Figure 10. Processor Package Drawing Sheet 3 of 3383.1.1 Processor Component Keep-Out Zones393.1.2 Package Loading Specifications39Table 20. Processor Loading Specifications393.1.3 Package Handling Guidelines39Table 21. Package Handling Guidelines393.1.4 Package Insertion Specifications403.1.5 Processor Mass Specification403.1.6 Processor Materials40Table 22. Processor Materials403.1.7 Processor Markings40Figure 11. Processor Top-Side Markings Example for the Intel® Core™2 Duo Desktop Processor E6000 Series with 4 MB L2 Cache with 1333 MHz FSB40Figure 12. Processor Top-Side Markings Example for the Intel® Core™2 Duo Desktop Processors E6000 Series with 4 MB L2 Cache with 1066 MHz FSB41Figure 13. Processor Top-Side Markings Example for the Intel® Core™2 Duo Desktop Processors E6000 Series with 2 MB L2 Cache41Figure 14. Processor Top-Side Markings Example for the Intel® Core™2 Duo Desktop Processors E4000 Series with 2 MB L2 Cache42Figure 15. Processor Top-Side Markings for the Intel® Core™2 Extreme Processor X6800423.1.8 Processor Land Coordinates43Figure 16. Processor Land Coordinates and Quadrants (Top View)434 Land Listing and Signal Descriptions454.1 Processor Land Assignments45Figure 17. land-out Diagram (Top View - Left Side)46Figure 18. land-out Diagram (Top View - Right Side)47Table 23. Alphabetical Land Assignments48Table 24. Numerical Land Assignment584.2 Alphabetical Signals Reference68Table 25. Signal Description (Sheet 1 of 9)685 Thermal Specifications and Design Considerations775.1 Processor Thermal Specifications775.1.1 Thermal Specifications77Table 26. Processor Thermal Specifications78Table 27. Thermal Profile 179Figure 19. Thermal Profile 179Table 28. Thermal Profile 280Figure 20. Thermal Profile 280Table 29. Thermal Profile 381Figure 21. Thermal Profile 381Table 30. Thermal Profile 482Figure 22. Thermal Profile 482Table 31. Thermal Profile 583Figure 23. Thermal Profile 5835.1.2 Thermal Metrology84Figure 24. Case Temperature (TC) Measurement Location845.2 Processor Thermal Features845.2.1 Thermal Monitor845.2.2 Thermal Monitor 285Figure 25. Thermal Monitor 2 Frequency and Voltage Ordering865.2.3 On-Demand Mode865.2.4 PROCHOT# Signal875.2.5 THERMTRIP# Signal875.3 Thermal Diode88Table 32. Thermal “Diode” Parameters using Diode Model88Table 33. Thermal “Diode” Parameters using Transistor Model89Table 34. Thermal Diode Interface895.4 Platform Environment Control Interface (PECI)905.4.1 Introduction90Figure 26. Processor PECI Topology905.4.1.1 Key Difference with Legacy Diode-Based Thermal Management90Figure 27. Conceptual Fan Control on PECI-Based Platforms91Figure 28. Conceptual Fan Control on Thermal Diode-Based Platforms915.4.2 PECI Specifications925.4.2.1 PECI Device Address925.4.2.2 PECI Command Support925.4.2.3 PECI Fault Handling Requirements925.4.2.4 PECI GetTemp0() Error Code Support92Table 35. GetTemp0() Error Codes926 Features936.1 Power-On Configuration Options93Table 36. Power-On Configuration Option Signals936.2 Clock Control and Low Power States93Figure 29. Processor Low Power State Machine946.2.1 Normal State946.2.2 HALT and Extended HALT Powerdown States946.2.2.1 HALT Powerdown State946.2.2.2 Extended HALT Powerdown State956.2.3 Stop Grant and Extended Stop Grant States956.2.3.1 Stop Grant State956.2.3.2 Extended Stop Grant State966.2.4 Extended HALT State, HALT Snoop State, Extended Stop Grant Snoop State, and Stop Grant Snoop State966.2.4.1 HALT Snoop State, Stop Grant Snoop State966.2.4.2 Extended HALT Snoop State, Extended Stop Grant Snoop State966.3 Enhanced Intel® SpeedStep® Technology967 Boxed Processor Specifications99Figure 30. Mechanical Representation of the Boxed Processor997.1 Mechanical Specifications1007.1.1 Boxed Processor Cooling Solution Dimensions100Figure 31. Space Requirements for the Boxed Processor (Side View)100Figure 32. Space Requirements for the Boxed Processor (Top View)100Figure 33. Space Requirements for the Boxed Processor (Overall View)1017.1.2 Boxed Processor Fan Heatsink Weight1017.1.3 Boxed Processor Retention Mechanism and Heatsink Attach Clip Assembly1017.2 Electrical Requirements1017.2.1 Fan Heatsink Power Supply101Figure 34. Boxed Processor Fan Heatsink Power Cable Connector Description102Table 37. Fan Heatsink Power and Signal Specifications102Figure 35. Baseboard Power Header Placement Relative to Processor Socket1037.3 Thermal Specifications1037.3.1 Boxed Processor Cooling Requirements103Figure 36. Boxed Processor Fan Heatsink Airspace Keepout Requirements (side 1 view)104Figure 37. Boxed Processor Fan Heatsink Airspace Keepout Requirements (Side 2 View)1047.3.2 Fan Speed Control Operation (Intel® Core2 Extreme Processor X6800 Only)1057.3.3 Fan Speed Control Operation (Intel® Core2 Duo Desktop Processor E6000 and E4000 Series Only)105Figure 38. Boxed Processor Fan Heatsink Set Points105Table 38. Fan Heatsink Power and Signal Specifications1068 Balanced Technology Extended (BTX) Boxed Processor Specifications107Figure 39. Mechanical Representation of the Boxed Processor with a Type I TMA107Figure 40. Mechanical Representation of the Boxed Processor with a Type II TMA1088.1 Mechanical Specifications1088.1.1 Balanced Technology Extended (BTX) Type I and Type II Boxed Processor Cooling Solution Dimensions108Figure 41. Requirements for the Balanced Technology Extended (BTX) Type I Keep-out Volumes109Figure 42. Requirements for the Balanced Technology Extended (BTX) Type II Keep-out Volume1108.1.2 Boxed Processor Thermal Module Assembly Weight1108.1.3 Boxed Processor Support and Retention Module (SRM)111Figure 43. Assembly Stack Including the Support and Retention Module1118.2 Electrical Requirements1128.2.1 Thermal Module Assembly Power Supply112Figure 44. Boxed Processor TMA Power Cable Connector Description112Table 39. TMA Power and Signal Specifications113Figure 45. Balanced Technology Extended (BTX) Mainboard Power Header Placement (hatched area)1138.3 Thermal Specifications1148.3.1 Boxed Processor Cooling Requirements1148.3.2 Variable Speed Fan114Figure 46. Boxed Processor TMA Set Points115Table 40. TMA Set Points for 3-wire operation of BTX Type I and Type II Boxed Processors1159 Debug Tools Specifications1179.1 Logic Analyzer Interface (LAI)1179.1.1 Mechanical Considerations1179.1.2 Electrical Considerations117Dimensioni: 1,72 MBPagine: 118Language: EnglishApri il manuale