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FH8065301487715

Scheda Tecnica (English)

Scheda Tecnica (FH8065301487715)

Sommario

Intel® Atom™ Processor E3800 Product Family
1
- Contents
  3
1 Introduction
27
- 1.1 Terminology
  29
- 1.2 Feature Overview
  30
2 Physical Interfaces
36
- 2.1 Pin States Through Reset
  38
- 2.2 System Memory Controller Interface Signals
  39
- 2.3 PCI Express* 2.0 Interface Signals
  41
- 2.4 USB 2.0 Host (EHCI/xHCI) Interface Signals
  41
- 2.5 USB 2.0 HSIC Interface Signals
  42
- 2.6 USB 3.0 (xHCI) Host Interface Signals
  42
- 2.7 USB 2.0 Device (ULPI) Interface Signals
  42
- 2.8 USB 3.0 Device Interface Signals
  43
- 2.9 Serial ATA (SATA) 2.0 Interface Signals
  44
- 2.10 Integrated Clock Interface Signals
  44
- 2.11 Display - Digital Display Interface (DDI) Signals
  45
- 2.12 Display – VGA Interface Signals
  46
- 2.13 MIPI Camera Serial Interface (CSI) and ISP Interface Signals
  46
- 2.14 Intel® High Definition Audio Interface Signals
  47
- 2.15 Low Power Engine (LPE) for Audio (I2S) Interface Signals
  47
- 2.16 Storage Control Cluster (eMMC, SDIO, SD) Interface Signals
  48
- 2.17 SIO – High Speed UART Interface Signals
  49
- 2.18 SIO – I2C Interface Signals
  50
- 2.19 SIO – Serial Peripheral Interface (SPI) Signals
  50
- 2.20 PCU – iLB – Real Time Clock (RTC) Interface Signals
  51
- 2.21 PCU – iLB – Low Pin Count (LPC) Bridge Interface Signals
  51
- 2.22 PCU – Serial Peripheral Interface (SPI) Signals
  52
- 2.23 PCU – System Management Bus (SMBus) Interface Signals
  53
- 2.24 PCU – Power Management Controller (PMC) Interface Signals
  53
- 2.25 JTAG and Debug Interface Signals
  54
- 2.26 Miscellaneous Signals
  54
- 2.27 GPIO Signals
  55
- 2.28 Power And Ground Pins
  59
- 2.29 Hardware Straps
  61
- 2.30 Configurable IO: GPIO Muxing
  62
- 2.31 Reserved Pins
  62
3 Register Access Methods
63
- 3.1 Fixed IO Register Access
  63
- 3.2 Fixed Memory Mapped Register Access
  63
- 3.3 IO Referenced Register Access
  63
- 3.4 Memory Referenced Register Access
  64
- 3.5 PCI Configuration Register Access
  64
- 3.6 Message Bus Register Access
  66
- 3.7 Register Field Access Types
  67
4 Mapping Address Spaces
69
- 4.1 Physical Address Space Mappings
  69
- 4.2 IO Address Space
  75
- 4.3 PCI Configuration Space
  76
5 Integrated Clock
79
- 5.1 Features
  80
6 Power Management
83
- 6.1 Power Management Features
  83
- 6.2 Power Management States Supported
  83
- 6.3 Processor Core Power Management
  88
- 6.4 Memory Controller Power Management
  94
- 6.5 PCI Express* (PCIe*) Power Management
  96
7 Power Up and Reset Sequence
97
- 7.1 SoC System States
  97
- 7.2 Power Up Sequences
  97
- 7.3 Power Down Sequences
  102
- 7.4 Reset Behavior
  105
8 Thermal Management
108
- 8.1 CPU Thermal Management Registers
  108
- 8.2 Thermal Sensors
  108
- 8.3 SoC Programmable Trips
  109
- 8.4 Platform Trips
  110
- 8.5 Thermal Throttling Mechanisms
  110
- 8.6 Thermal Status
  110
9 Electrical Specifications
111
- 9.1 Thermal Specifications
  111
- 9.2 Storage Conditions
  112
- 9.3 Voltage and Current Specifications
  113
- 9.4 Crystal Specifications
  123
- 9.5 DC Specifications
  124
- 9.6 AC Specifications
  146
10 Ballout and Package Information
207
- 10.1 SoC Attributes
  207
- 10.2 Package Diagrams
  208
- 10.3 Ball Name and Function by Location
  210
- 10.4 Alphabetical Ball Name List
  258
11 Processor Core
269
- 11.1 Features
  269
- 11.2 Platform Identification and CPUID
  272
- 11.3 References
  273
12 System Memory Controller
274
- 12.1 Signal Descriptions
  274
- 12.2 Features
  278
- 12.3 System Memory Controller (D-Unit) Message Registers
  281
13 SoC Transaction Router
316
- 13.1 Transaction Router A-Unit Message Registers
  318
- 13.2 SoC Transaction Router PCI Config Access IO Registers
  321
- 13.3 Transaction Router B-Unit Message Registers
  323
- 13.4 Transaction Router C-Unit PCI Registers
  338
- 13.5 Transaction Router C-Unit Message Registers
  345
- 13.6 Transaction Router P-Unit Message Registers
  351
14 Graphics, Video and Display
405
- 14.1 Features
  405
- 14.2 SoC Graphics Display
  406
- 14.3 Display Pipes
  407
- 14.4 Display Physical Interfaces
  407
- 14.5 References
  413
- 14.6 3D Graphics and Video
  413
- 14.7 Features
  414
- 14.8 VED (Video Encode/Decode)
  416
- 14.9 PCI Configuration Registers
  419
- 14.10 Memory Mapped Registers (1 of 2)
  445
- 14.11 Memory Mapped Registers (2 of 2)
  635
- 14.12 Memory Mapped Registers (Read Only)
  1027
- 14.13 Memory Mapped Registers (Write Only)
  1033
15 MIPI-Camera Serial Interface (CSI) and ISP
1037
- 15.1 Signal Descriptions
  1037
- 15.2 Features
  1039
- 15.3 Imaging Subsystem Integration
  1042
- 15.4 Functional Description
  1044
- 15.5 MIPI-CSI-2 Receiver
  1046
- 15.6 Register Map
  1048
- 15.7 Image Signal Processor PCI Configuration Registers
  1050
- 15.8 Image Signal Processor Memory Mapped IO Registers
  1076
16 Storage Control Cluster (eMMC, SDIO, SD Card)
1744
- 16.1 Signal Descriptions
  1744
- 16.2 Features
  1746
- 16.3 References
  1748
- 16.4 Register Map
  1749
- 16.5 SDIO for Wifi PCI Configuration Registers
  1751
- 16.6 SDIO for Wifi Memory Mapped IO Registers
  1763
- 16.7 SD Card PCI Configuration Registers
  1807
- 16.8 SD Card Memory Mapped IO Registers
  1819
- 16.9 eMMC 4.5 PCI Configuration Registers
  1863
- 16.10 eMMC 4.5 Memory Mapped IO Registers
  1875
17 Serial ATA (SATA)
1919
- 17.1 Signal Descriptions
  1919
- 17.2 Features
  1920
- 17.3 References
  1922
- 17.4 Register Map
  1923
- 17.5 SATA PCI Configuration Registers
  1924
- 17.6 SATA Legacy IO Registers
  1953
- 17.7 SATA Index Pair IO Registers
  1959
- 17.8 SATA AHCI Memory Mapped IO Registers
  1961
- 17.9 SATA Primary Read Command IO Registers
  1998
- 17.10 SATA Primary Write Command IO Registers
  2003
- 17.11 SATA Primary Read Control IO Registers
  2005
- 17.12 SATA Primary Write Control IO Registers
  2006
- 17.13 SATA Secondary Read Command IO Registers
  2007
- 17.14 SATA Secondary Write Command IO Registers
  2012
- 17.15 SATA Secondary Read Control IO Registers
  2014
- 17.16 SATA Secondary Write Control IO Registers
  2015
- 17.17 SATA Lane 0 Electrical Register Address Map
  2017
- 17.18 SATA Lane 0 Electrical Register Address Map
  2047
- 17.19 SATA Lane 1 Electrical Register Address Map
  2065
- 17.20 SATA Lane 1 Electrical Register Address Map
  2095
18 USB Host Controller Interfaces (xHCI, EHCI)
2112
- 18.1 Signal Descriptions
  2112
- 18.2 USB 3.0 xHCI (Extensible Host Controller Interface)
  2114
- 18.3 USB 2.0 Enhanced Host Controller Interface (EHCI)
  2115
- 18.4 References
  2116
- 18.5 Register Map
  2117
- 18.6 USB xHCI PCI Configuration Registers
  2120
- 18.7 USB xHCI Memory Mapped I/O Registers
  2163
- 18.8 USB EHCI PCI Configuration Registers
  2345
- 18.9 USB EHCI Memory Mapped IO Registers
  2369
- 18.10 USB EHCI Electrical Message Bus Registers
  2427
19 USB Device Controller Interfaces (3.0, ULPI)
2443
- 19.1 USB Device Controller
  2445
- 19.2 References
  2446
- 19.3 Register Map
  2446
- 19.4 USB 3.0 Device PCI Configuration Registers
  2447
- 19.5 USB 3.0 Device PCI Configuration Registers
  2456
- 19.6 USB 3.0 Device Memory Mapped I/O Registers
  2461
- 19.7 USB 3.0 Device Memory Mapped I/O Registers
  2642
20 Intel® High Definition Audio
2662
- 20.1 Signal Descriptions
  2663
- 20.2 Features
  2664
- 20.3 References
  2664
- 20.4 Register Map
  2665
- 20.5 HD Audio PCI Configuration Registers
  2667
- 20.6 HD Audio Memory Mapped I/O Registers
  2698
21 Low Power Engine (LPE) for Audio (I2S)
2798
- 21.1 Signal Descriptions
  2798
- 21.2 Features
  2799
- 21.3 Detailed Block Level Description
  2800
- 21.4 Software Implementation Considerations
  2803
- 21.5 Clocks
  2805
- 21.6 SSP (I2S)
  2808
- 21.7 Programming Model
  2813
- 21.8 Register Map
  2818
- 21.9 Low Power Audio PCI Configuration Registers
  2819
- 21.10 pci_mem Address Map
  2827
- 21.11 Memory Mapped Shim Registers
  2837
- 21.12 Low Power Audio I2S0 Address Map
  2864
- 21.13 Low Power Audio I2S0 Address Map
  2884
- 21.14 Low Power Audio I2S0 Address Map
  2904
- 21.15 Low Power Audio DMA0 Memory Mapped IO Registers
  2924
- 21.16 Low Power Audio DMA1 Memory Mapped IO Registers
  3037
22 Intel® Trusted Execution Engine (TXE)
3150
- 22.1 Features
  3150
- 22.2 Register Map
  3151
- 22.3 Intel® TXE PCI Configuration Registers
  3153
23 PCI Express* 2.0
3179
- 23.1 Signal Descriptions
  3179
- 23.2 Features
  3180
- 23.3 References
  3183
- 23.4 Register Map
  3183
- 23.5 PCI Configuration Registers
  3185
- 23.6 PCI Express* PCI Configuration Registers
  3186
- 23.7 PCI Express* Lane 0 Electrical Address Map
  3229
- 23.8 PCI Express* Lane 0 Electrical Address Map
  3259
- 23.9 PCI Express* Lane 1 Electrical Address Map
  3277
- 23.10 PCI Express* Lane 1 Electrical Address Map
  3307
- 23.11 PCI Express* Lane 2 Electrical Address Map
  3325
- 23.12 PCI Express* Lane 2 Electrical Address Map
  3355
- 23.13 PCI Express* Lane 3 Electrical Address Map
  3373
- 23.14 PCI Express* Lane 3 Electrical Address Map
  3403
24 Serial IO (SIO) Overview
3420
- 24.1 Serial I/O (SIO) Register Map
  3420
- 24.2 SIO DMA PCI Configuration Registers for SPI, HSUART, PWM
  3421
- 24.3 SIO DMA Memory Mapped I/O Registers for SPI, HSUART, PWM
  3430
- 24.4 SIO DMA PCI Configuration Registers for I2C
  3604
- 24.5 SIO DMA Memory Mapped I/O Registers for I2C
  3613
25 SIO – Serial Peripheral Interface (SPI)
3788
- 25.1 Signal Descriptions
  3788
- 25.2 Features
  3789
- 25.3 Register Map
  3792
- 25.4 SIO SPI PCI Configuration Registers
  3793
- 25.5 SIO SPI Memory Mapped I/O Registers
  3802
26 SIO - I2C Interface
3819
- 26.1 Signal Descriptions
  3819
- 26.2 Features
  3820
- 26.3 Use
  3826
- 26.4 References
  3828
- 26.5 Register Map
  3828
- 26.6 SIO I2C 0 PCI Configuration Registers
  3830
- 26.7 SIO I2C 0 Memory Mapped I/O Registers
  3839
- 26.8 SIO I2C 1 PCI Configuration Registers
  3878
- 26.9 SIO I2C 1 PCI Configuration Registers
  3888
- 26.10 SIO I2C 2 PCI Configuration Registers
  3927
- 26.11 SIO I2C 2 Memory Mapped I/O Registers
  3937
- 26.12 SIO I2C 3 PCI Configuration Registers
  3976
- 26.13 SIO I2C 3 Memory Mapped I/O Registers
  3986
- 26.14 SIO I2C 4 PCI Configuration Registers
  4025
- 26.15 SIO I2C 4 Memory Mapped I/O Registers
  4035
- 26.16 SIO I2C 5 PCI Configuration Registers
  4074
- 26.17 SIO I2C 5 Memory Mapped I/O Registers
  4084
- 26.18 SIO I2C 6 PCI Configuration Registers
  4123
- 26.19 SIO I2C 6 Memory Mapped I/O Registers
  4133
27 SIO – High Speed UART
4172
- 27.1 Signal Descriptions
  4172
- 27.2 Features
  4173
- 27.3 Use
  4175
- 27.4 Register Map
  4176
- 27.5 SIO HSUART 0 PCI Configuration Registers
  4178
- 27.6 SIO HSUART 0 Memory Mapped I/O Registers
  4187
- 27.7 SIO HSUART 1 PCI Configuration Registers
  4220
- 27.8 SIO HSUART 0 Memory Mapped I/O Registers
  4229
28 SIO – Pulse Width Modulation (PWM)
4262
- 28.1 Signal Descriptions
  4262
- 28.2 Features
  4263
- 28.3 Use
  4264
- 28.4 Register Map
  4264
- 28.5 SIO PWM 0 PCI Configuration Registers
  4266
- 28.6 SIO PWM 0 Memory Mapped I/O Registers
  4275
- 28.7 SIO PWM 1 PCI Configuration Registers
  4278
- 28.8 SIO PWM 1 Memory Mapped I/O Registers
  4287
29 Platform Controller Unit (PCU) Overview
4290
- 29.1 Features
  4290
- 29.2 PCU iLB LPC Port 80h I/O Registers
  4292
30 PCU – Power Management Controller (PMC)
4299
- 30.1 Signal Descriptions
  4299
- 30.2 Features
  4301
- 30.3 USB Per-Port Register Write Control
  4310
- 30.4 References
  4310
- 30.5 Register Map
  4310
- 30.6 PCU PMC Memory Mapped I/O Registers
  4311
- 30.7 PCU PMC IO Registers
  4345
- 30.8 PCU iLB PMC I/O Registers
  4348
31 PCU – Serial Peripheral Interface (SPI)
4365
- 31.1 Signal Descriptions
  4365
- 31.2 Features
  4366
- 31.3 Use
  4378
- 31.4 Register Map
  4380
- 31.5 PCU SPI for Firmware Memory Mapped I/O Registers
  4381
32 PCU – Universal Asynchronous Receiver/Transmitter (UART)
4415
- 32.1 Signal Descriptions
  4415
- 32.2 Features
  4416
- 32.3 Use
  4418
- 32.4 UART Enable/Disable
  4418
- 32.5 IO Mapped Registers
  4419
- 32.6 PCU iLB UART IO Registers
  4420
33 PCU – System Management Bus (SMBus)
4429
- 33.1 Signal Descriptions
  4429
- 33.2 Features
  4430
- 33.3 Use
  4438
- 33.4 References
  4438
- 33.5 Register Map
  4438
- 33.6 PCU SMBUS PCI Configuration Registers
  4440
- 33.7 PCU SMBUS Memory Mapped I/O Registers
  4454
- 33.8 PCU SMBUS I/O Registers
  4466
34 PCU – Intel® Legacy Block (iLB) Overview
4478
- 34.1 Signal Descriptions
  4478
- 34.2 Features
  4479
- 34.3 PCU iLB Interrupt Decode and Route
  4481
35 PCU – iLB – Low Pin Count (LPC) Bridge
4515
- 35.1 Signal Descriptions
  4515
- 35.2 Features
  4516
- 35.3 Use
  4521
- 35.4 References
  4523
- 35.5 Register Map
  4523
- 35.6 PCU iLB Low Pin Count (LPC) Bridge PCI Configuration Registers
  4525
- 35.7 PCU iLB LPC BIOS Control Memory Mapped I/O Registers
  4542
36 PCU – iLB – Real Time Clock (RTC)
4543
- 36.1 Signal Descriptions
  4543
- 36.2 Features
  4544
- 36.3 Interrupts
  4545
- 36.4 References
  4547
- 36.5 Register Map
  4547
- 36.6 IO Mapped Registers
  4547
- 36.7 Indexed Registers
  4547
- 36.8 PCU iLB Real Time Clock (RTC) I/O Registers
  4549
37 PCU – iLB – 8254 Timers
4551
- 37.1 Signal Descriptions
  4551
- 37.2 Features
  4552
- 37.3 Use
  4552
- 37.4 Register Map
  4555
- 37.5 IO Mapped Registers
  4555
- 37.6 PCU iLB 8254 Timers IO Registers
  4556
38 PCU – iLB – High Precision Event Timer (HPET)
4561
- 38.1 Features
  4561
- 38.2 References
  4563
- 38.3 Register Map
  4563
- 38.4 Memory Mapped Registers
  4563
- 38.5 PCU iLB High Performance Event Timer (HPET) Memory Mapped IO Registers
  4564
39 PCU – iLB – GPIO
4572
- 39.1 Signal Descriptions
  4572
- 39.2 Features
  4572
- 39.3 Legacy Use
  4573
- 39.4 Memory Mapped Use
  4573
- 39.5 Register Map
  4574
- 39.6 GPIO Registers
  4575
- 39.7 PCU iLB GPIO S0 IO Addressed Registers
  4577
- 39.8 PCU iLB GPIO S0 Memory Addressed Registers
  4601
- 39.9 PCU iLB GPIO S5 IO Addressed Registers
  5045
- 39.10 PCU iLB GPIO S5 Memory Address Map
  5059
40 PCU – iLB – Interrupt Decoding and Routing
5282
- 40.1 Features
  5282
41 PCU – iLB – IO APIC
5284
- 41.1 Features
  5284
- 41.2 Use
  5286
- 41.3 Indirect I/O APIC Registers
  5287
- 41.4 PCU iLB IO APIC Memory Mapped I/O Registers
  5288
42 PCU – iLB – 8259 Programmable Interrupt Controllers (PIC)
5290
- 42.1 Features
  5290
- 42.2 IO Mapped Registers
  5297
- 42.3 PCU iLB 8259 Interrupt Controller (PIC) I/O Registers
  5299

Scheda Tecnica (FH8065301487715)

Dimensioni:

97,8 MB
Pagine:

5308
Language:

English

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