Manuali utente per Intel G2120T

Sommario

• 1 Introduction

  9
  • 1.1 Processor Feature Details

    11
    • 1.1.1 Supported Technologies

      11
  • 1.2 Interfaces

    11
    • 1.2.1 System Memory Support

      11
    • 1.2.2 PCI Express*

      12
    • 1.2.3 Direct Media Interface (DMI)

      13
    • 1.2.4 Platform Environment Control Interface (PECI)

      14
    • 1.2.5 Intel® HD Graphics

      14
    • 1.2.6 Intel® Flexible Display Interface (Intel® FDI)

      14
  • 1.3 Power Management Support

    15
    • 1.3.1 Processor Core

      15
    • 1.3.2 System

      15
    • 1.3.3 Memory Controller

      15
    • 1.3.4 PCI Express*

      15
  • 1.4 Thermal Management Support

    15
  • 1.5 Package

    15
  • 1.6 Terminology

    15
  • 1.7 Related Documents

    18
• 2 Interfaces

  19
  • 2.1 System Memory Interface

    19
    • 2.1.1 System Memory Technology Supported

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    • 2.1.2 System Memory Timing Support

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    • 2.1.3 System Memory Organization Modes

      21
      • 2.1.3.1 Single-Channel Mode

        21
      • 2.1.3.2 Dual-Channel Mode—Intel® Flex Memory Technology Mode

        21
    • 2.1.4 Rules for Populating Memory Slots

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    • 2.1.5 Technology Enhancements of Intel® Fast Memory Access (Intel® FMA)

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      • 2.1.5.1 Just-in-Time Command Scheduling

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      • 2.1.5.2 Command Overlap

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      • 2.1.5.3 Out-of-Order Scheduling

        23
    • 2.1.6 System Memory Pre-Charge Power Down Support Details

      23
  • 2.2 PCI Express* Interface

    24
    • 2.2.1 PCI Express* Architecture

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      • 2.2.1.1 Transaction Layer

        25
      • 2.2.1.2 Data Link Layer

        25
      • 2.2.1.3 Physical Layer

        25
    • 2.2.2 PCI Express* Configuration Mechanism

      26
    • 2.2.3 PCI Express Port

      26
  • 2.3 Direct Media Interface (DMI)

    27
    • 2.3.1 DMI Error Flow

      27
    • 2.3.2 Processor/PCH Compatibility Assumptions

      27
    • 2.3.3 DMI Link Down

      27
  • 2.4 Integrated Graphics

    27
    • 2.4.1 3D and Video Engines for Graphics Processing

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      • 2.4.1.1 3D Engine Execution Units (EUs)

        28
      • 2.4.1.2 3D Pipeline

        28
      • 2.4.1.3 Video Engine

        29
      • 2.4.1.4 2D Engine

        29
    • 2.4.2 Integrated Graphics Display

      31
      • 2.4.2.1 Display Planes

        31
      • 2.4.2.2 Display Pipes

        32
      • 2.4.2.3 Display Ports

        32
    • 2.4.3 Intel® Flexible Display Interface

      32
  • 2.5 Platform Environment Control Interface (PECI)

    33
  • 2.6 Interface Clocking

    33
    • 2.6.1 Internal Clocking Requirements

      33
• 3 Technologies

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  • 3.1 Intel® Virtualization Technology

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    • 3.1.1 Intel® VT-x Objectives

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    • 3.1.2 Intel® VT-x Features

      35
    • 3.1.3 Intel® VT-d Objectives

      36
    • 3.1.4 Intel® VT-d Features

      36
    • 3.1.5 Intel® VT-d Features Not Supported

      37
  • 3.2 Intel® Trusted Execution Technology (Intel® TXT)

    37
  • 3.3 Intel® Hyper-Threading Technology

    38
  • 3.4 Intel® Turbo Boost Technology

    38
  • 3.5 New Instructions

    38
    • 3.5.1 Advanced Encryption Standard New Instructions (AESNI)

      38
    • 3.5.2 PCLMULQDQ Instruction

      38
• 4 Power Management

  39
  • 4.1 ACPI States Supported

    39
    • 4.1.1 System States

      39
    • 4.1.2 Processor Core/Package Idle States

      39
    • 4.1.3 Integrated Memory Controller States

      39
    • 4.1.4 PCI Express* Link States

      40
    • 4.1.5 Integrated Graphics States

      40
    • 4.1.6 Interface State Combinations

      40
  • 4.2 Processor Core Power Management

    41
    • 4.2.1 Enhanced Intel® SpeedStep® Technology

      41
    • 4.2.2 Low-Power Idle States

      41
    • 4.2.3 Requesting Low-Power Idle States

      43
    • 4.2.4 Core C-states

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      • 4.2.4.1 Core C0 State

        44
      • 4.2.4.2 Core C1/C1E State

        44
      • 4.2.4.3 Core C3 State

        44
      • 4.2.4.4 Core C6 State

        44
      • 4.2.4.5 C-State Auto-Demotion

        45
    • 4.2.5 Package C-States

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      • 4.2.5.1 Package C0

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      • 4.2.5.2 Package C1/C1E

        47
      • 4.2.5.3 Package C3 State

        47
      • 4.2.5.4 Package C6 State

        47
  • 4.3 Integrated Memory Controller (IMC) Power Management

    48
    • 4.3.1 Disabling Unused System Memory Outputs

      48
    • 4.3.2 DRAM Power Management and Initialization

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      • 4.3.2.1 Initialization Role of CKE

        48
      • 4.3.2.2 Conditional Self-Refresh

        48
      • 4.3.2.3 Dynamic Power Down Operation

        49
      • 4.3.2.4 DRAM I/O Power Management

        49
  • 4.4 PCI Express* Power Management

    49
  • 4.5 Integrated Graphics Power Management

    50
    • 4.5.1 Graphics Render C-State

      50
• 5 Thermal Management

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• 6 Signal Description

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  • 6.1 System Memory Interface

    54
  • 6.2 Memory Reference and Compensation

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  • 6.3 Reset and Miscellaneous Signals

    56
  • 6.4 PCI Express* Based Interface Signals

    58
  • 6.5 DMI—Processor to PCH Serial Interface

    58
  • 6.6 PLL Signals

    58
  • 6.7 Intel® Flexible Display Interface Signals

    59
  • 6.8 JTAG/ITP Signals

    59
  • 6.9 Error and Thermal Protection

    60
  • 6.10 Power Sequencing

    61
  • 6.11 Processor Core Power Signals

    61
  • 6.12 Graphics and Memory Core Power Signals

    63
  • 6.13 Ground and NCTF

    63
  • 6.14 Processor Internal Pull Up/Pull Down

    64
• 7 Electrical Specifications

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  • 7.1 Power and Ground Lands

    65
  • 7.2 Decoupling Guidelines

    65
    • 7.2.1 Voltage Rail Decoupling

      65
  • 7.3 Processor Clocking (BCLK[0], BCLK#[0])

    66
    • 7.3.1 PLL Power Supply

      66
  • 7.4 VCC Voltage Identification (VID)

    66
  • 7.5 Graphics Voltage Identification (GFX_VID)

    67
  • 7.6 Reserved or Unused Signals

    70
  • 7.7 Signal Groups

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  • 7.8 Test Access Port (TAP) Connection

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  • 7.9 Absolute Maximum and Minimum Ratings

    73
  • 7.10 DC Specifications

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    • 7.10.1 Voltage and Current Specifications

      74
  • 7.11 Platform Environmental Control Interface (PECI) DC Specifications

    82
    • 7.11.1 DC Characteristics

      82
    • 7.11.2 Input Device Hysteresis

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• 8 Processor Land and Signal Information

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  • 8.1 Processor Land Assignments

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