Scheda Tecnica (AD80583JH046003)Sommario1 Introduction91.1 Terminology111.2 State of Data131.3 References132 Electrical Specifications152.1 Front Side Bus and GTLREF152.2 Decoupling Guidelines162.2.1 VCC Decoupling162.2.2 VTT Decoupling162.2.3 Front Side Bus AGTL+ Decoupling162.3 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking162.3.1 Front Side Bus Frequency Select Signals (BSEL[2:0])172.3.2 PLL Power Supply182.4 Voltage Identification (VID)182.5 Reserved, Unused, or Test Signals202.6 Front Side Bus Signal Groups202.7 CMOS Asynchronous and Open Drain Asynchronous Signals222.8 Test Access Port (TAP) Connection222.9 Mixing Processors232.10 Absolute Maximum and Minimum Ratings232.11 Processor DC Specifications242.11.1 Flexible Motherboard Guidelines (FMB)242.11.2 VCC Overshoot Specification332.11.3 Die Voltage Validation332.11.4 Platform Environmental Control Interface (PECI) DC Specifications342.12 AGTL+ FSB Specifications352.13 Front Side Bus AC Specifications372.14 Processor AC Timing Waveforms413 Mechanical Specifications513.1 Package Mechanical Drawing513.2 Processor Component Keepout Zones543.3 Package Loading Specifications603.4 Package Handling Guidelines613.5 Package Insertion Specifications613.6 Processor Mass Specifications613.7 Processor Materials613.8 Processor Markings623.9 Processor Pin-Out Coordinates634 Pin Listing654.1 Processor Pin Assignments654.1.1 Pin Listing by Pin Name654.1.2 Pin Listing by Pin Number735 Signal Definitions815.1 Signal Definitions816 Thermal Specifications896.1 Package Thermal Specifications896.1.1 Thermal Specifications896.1.2 Thermal Metrology976.2 Processor Thermal Features976.2.1 Intel® Thermal Monitor Features976.2.2 Intel Thermal Monitor976.2.3 Intel Thermal Monitor 2986.2.4 On-Demand Mode996.2.5 PROCHOT# Signal1006.2.6 FORCEPR# Signal1006.2.7 THERMTRIP# Signal1006.3 Platform Environment Control Interface (PECI)1016.3.1 Introduction1016.3.2 PECI Specifications1037 Features1057.1 Power-On Configuration Options1057.2 Clock Control and Low Power States1057.2.1 Normal State1067.2.2 HALT or Extended HALT State1067.2.3 Stop-Grant State1087.2.4 Extended HALT Snoop or HALT Snoop State, Stop Grant Snoop State1097.3 Enhanced Intel SpeedStep® Technology1097.4 System Management Bus (SMBus) Interface1107.4.1 SMBus Device Addressing1117.4.2 PIROM and Scratch EEPROM Supported SMBus Transactions1127.4.3 Processor Information ROM (PIROM)1137.4.4 Checksums1327.4.5 Scratch EEPROM1328 Debug Tools Specifications1338.1 Debug Port System Requirements1338.2 Logic Analyzer Interface (LAI)1338.2.1 Mechanical Considerations1338.2.2 Electrical Considerations1349 Boxed Processor Specifications1359.1 Introduction1359.2 Thermal Specifications1359.2.1 Boxed Processor Cooling Requirements135Dimensioni: 2,77 MBPagine: 136Language: EnglishApri il manuale