Manuale UtenteSommarioContents7List of Figures11List of Tables13List of Examples15Using This Guide17Purpose17Audience17Byte Ordering and Bit Coding Convention18Type Definition18Code Examples18Icon Conventions18Text Conventions19Checking and Downloading from the Interphase WWW/FTP Site20WWW Method20FTP Method20Hardware Description23Overview234538 Hardware Structure24The PowerQUICC II24PowerQUICC II Resets25System Clocks26PCI Local Space Mapping26Interrupts29Memory Controllers29Communication Processor Module (CPM) I/O Ports30CPM TDM Busses32Bank of Clocks33Baud Rate Generator33Ethernet 10/100BaseT33TTY Console Serial Port34User-Programmable LEDs34The PCI Bridge35PowerSpan PCI Configuration Registers36PowerSpan PCI Registers37PowerSpan Processor Bus Registers38PowerSpan DMA Registers39PowerSpan Miscellaneous Registers40PowerSpan I·O Registers41Interrupt Pins and Doorbell Usage41PCI to Local Interrupt (ATN)42Local to PCI Interrupt (–INTA)43Hardware and Software Resets Through the PowerSpan43Local Space Access From PCI Memory Space43Access to the FLASH EEPROM Through CompactPCI46PCI Memory Space and I/O Space Access From the PowerQUICC II46In-situ EPLDs Programming48Serial EEPROM Connected to the PowerSpan49Board Equipment Register49Vital Product Data (VPD)51Interphase-Specific Production Data and Boot Monitor Parameters51The FLASH EEPROM Boot Memory51The QuadFALC T1/E1/J1 Framer52The Ethernet Transceiver55TDM Bus Configurations56General56Multiplex Direct Mode60Independent Direct Mode64Switched Mode70Pass-Through Mode744538 Power-Up Initialization81Overview81PowerSpan Initialization81PowerSpan Hardware Configuration Word81PowerSpan Register Initialization Through the I·C Serial EEPROM82Other PowerSpan Initializations83PowerQUICC II Hardware Configuration Word84PowerQUICC II Initializations85PowerQUICC II System Interface Unit (SIU) Initialization85Internal Memory Map Register (IMMR)85Bus Configuration Register (BCR)85System Protection Control Register (SYPCR)8660x Bus Arbiter Registers (PPC_ACR, PPC_ALRH, and PPC_ALRL)86SIU Module Configuration Register (SIUMCR)86Bus Transfer Error Registers (TESCR1 and L_TESCR1)87Memory Controllers87SDRAM Controller and SDRAM Device Initialization87GPCM Controller Initialization88UPM Controller Programming88MPC603e Core Initialization88MMU Initialization88Cache Initialization88Communication Processor Module Initialization89I/O Port Initialization89CPM RCCR Reset89Programming the Peripherals91Overview91PowerQUICC II CPM Initialization91Serial Interfaces and Time Slot Assigner Initialization91TDM Busses in Multiplexed Direct Mode and in Switched Mode91TDM Busses in Independent Direct Mode92TDM Busses in Pass-Through Mode93Clocks and Baud-Rate Generators95Introduction95BRGCLK95BRG7 – TTY Baud-Rate Generator95MCC Initialization95T1/E1/J1 Framer Initialization97Introduction97Master Clock Initialization97TDM Busses General Structure97Multiplexed Direct Mode98Independent Direct Mode100Switched Mode101Pass-Through Mode102Framing and Line Coding Initialization104Common Initialization104T1 Specific Initialization104E1/E1-CRC4 Common Initialization104E1 Non-CRC4 Specific Initialization105E1-CRC4 Specific Initialization105Clock Synchronization Initialization105Transmit Pulse Shape106Line LED Control106The Ethernet Port Initialization106The TTY Framer Initialization106Accessing the 4538 on the PCI Side109PowerSpan Configuration by the PCI Host109PCI Configuration109Interrupt Pin Configuration109PCI-to-Local Window Configuration109Controlling the 4538 Hardware and Software Resets109Controlling the PCI-to-Local Interrupt110Local to PCI Interrupt (–INTA)111Local Space Access From PCI Memory Space111Access to the FLASH EEPROM Through PCI112FLASH EEPROM Programming Algorithms114Serial EEPROM Connected to the PowerSpan114In Situ EPLD Programming115Optimizing the PCI Bus Utilization115Effective Ordering of the PCI Accesses115PCI Deadlock Situations116Connectors and Front Panel117Connector Placement117Front Panel118LED Descriptions118RJ48 Connectors J1 and J2118Ethernet 10/100 RJ45 Connector J3119TTY Serial Port J4120PMC Connectors120PMC Connectors P1 and P2120PMC Connector P4125Debug Port J5127ISP Enable Jumper JP1128Blank Card Jumper JP2128Connector Summary129Carrier Card Specification129CompactPCI Carrier Card129Custom Carrier Card1316435 Rear Transition Module132Mechanical Information135PMC Card Dimensions135Carrier Card Dimension Requirements136Bibliography137Industry Standards137Telecommunication Standards138Manufacturers’ Documents140Glossary143Index149Dimensioni: 1,21 MBPagine: 149Language: EnglishApri il manuale