Manuali utente per LSI 53C875A

Sommario

• LSI53C875A PCI to Ultra SCSI

  1
• Controller

  1
  • Chapter1 General Description

    15
    • Figure1.1 Typical LSI53C875A System Application

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    • Figure1.2 Typical LSI53C875A Board Application

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    • 1.1 New Features in the LSI53C875A

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    • 1.2 Benefits of Ultra SCSI

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    • 1.3 TolerANT® Technology

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    • 1.4 LSI53C875A Benefits Summary

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      • 1.4.1 SCSI Performance

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      • 1.4.2 PCI Performance

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      • 1.4.3 Integration

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      • 1.4.4 Ease of Use

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      • 1.4.5 Flexibility

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      • 1.4.6 Reliability

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      • 1.4.7 Testability

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  • Chapter2 Functional Description

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    • Figure2.1 LSI53C875A Block Diagram

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    • 2.1 PCI Functional Description

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      • 2.1.1 PCI Addressing

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      • 2.1.2 PCI Bus Commands and Functions Supported

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        • Table 2.1 PCI Bus Commands and Encoding Types for the LSI53C875A

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      • 2.1.3 PCI Cache Mode

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        • Table 2.2 PCI Cache Mode Alignment

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    • 2.2 SCSI Functional Description

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      • 2.2.1 SCRIPTS Processor

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      • 2.2.2 Internal SCRIPTS RAM

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      • 2.2.3 64-Bit Addressing in SCRIPTS

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      • 2.2.4 Hardware Control of SCSI Activity LED

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      • 2.2.5 Designing an Ultra SCSI System

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      • 2.2.6 Prefetching SCRIPTS Instructions

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      • 2.2.7 Opcode Fetch Burst Capability

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      • 2.2.8 Load and Store Instructions

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      • 2.2.9 JTAG Boundary Scan Testing

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      • 2.2.10 SCSI Loopback Mode

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      • 2.2.11 Parity Options

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        • Table 2.3 Bits Used for Parity Control and Generation

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        • Table 2.4 SCSI Parity Control

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        • Table 2.5 SCSI Parity Errors and Interrupts

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        • Figure2.2 Parity Checking/Generation

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      • 2.2.12 DMA FIFO

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        • Figure2.3 DMA FIFO Sections

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        • Figure2.4 LSI53C875A Host Interface SCSI Data Paths

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      • 2.2.13 SCSI Bus Interface

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        • Figure2.5 Regulated Termination for Ultra SCSI

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      • 2.2.14 Select/Reselect During Selection/Reselection

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      • 2.2.15 Synchronous Operation

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        • Figure2.6 Determining the Synchronous Transfer Rate

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      • 2.2.16 Interrupt Handling

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      • 2.2.17 Chained Block Moves

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        • Figure2.7 Block Move and Chained Block Move Instructions

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    • 2.3 Parallel ROM Interface

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      • Table 2.6 Parallel ROM Support

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    • 2.4 Serial EEPROM Interface

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      • 2.4.1 Default Download Mode

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        • Table 2.7 Mode A Serial EEPROM Data Format

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      • 2.4.2 No Download Mode

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    • 2.5 Power Management

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      • Table 2.8 Power States

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      • 2.5.1 Power State D0

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      • 2.5.2 Power State D1

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      • 2.5.3 Power State D2

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      • 2.5.4 Power State D3

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  • Chapter3 Signal Descriptions

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    • 3.1 LSI53C875A Functional Signal Grouping

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      • Figure3.1 LSI53C875A Functional Signal Grouping

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    • 3.2 Signal Descriptions

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      • 3.2.1 Internal Pull-ups on LSI53C875A Signals

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        • Table 3.1 LSI53C875A Internal Pull-ups

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    • 3.3 PCI Bus Interface Signals

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      • 3.3.1 System Signals

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        • Table 3.2 System Signals

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      • 3.3.2 Address and Data Signals

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        • Table 3.3 Address and Data Signals

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      • 3.3.3 Interface Control Signals

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        • Table 3.4 Interface Control Signals

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      • 3.3.4 Arbitration Signals

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        • Table 3.5 Arbitration Signals

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      • 3.3.5 Error Reporting Signals

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        • Table 3.6 Error Reporting Signals

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      • 3.3.6 Interrupt Signal

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        • Table 3.7 Interrupt Signal

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    • 3.4 SCSI Bus Interface Signals

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      • 3.4.1 SCSI Bus Interface Signal

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        • Table 3.8 SCSI Bus Interface Signal

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      • 3.4.2 SCSI Signals

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        • Table 3.9 SCSI Signals

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      • 3.4.3 SCSI Control Signals

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        • Table 3.10 SCSI Control Signals

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    • 3.5 GPIO Signals

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      • Table 3.11 GPIO Signals

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    • 3.6 ROM Flash and Memory Interface Signals

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      • Table 3.12 ROM Flash and Memory Interface Signals

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    • 3.7 Test Interface Signals

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      • Table 3.13 Test Interface Signals

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    • 3.8 Power and Ground Signals

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      • Table 3.14 Power and Ground Signals

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    • 3.9 MAD Bus Programming

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      • Table 3.15 Decode of MAD Pins

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  • Chapter4 Registers

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    • 4.1 PCI Configuration Registers

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      • Table 4.1 PCI Configuration Register Map

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    • 4.2 SCSI Registers

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      • Table 4.2 SCSI Register Address Map

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      • Table 4.3 Examples of Synchronous Transfer Periods and Rates for SCSI-1

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      • Table 4.4 Example Transfer Periods and Rates for Fast SCSI-2 and Ultra SCSI

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      • Table 4.5 Maximum Synchronous Offset

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      • Table 4.6 SCSI Synchronous Data FIFO Word Count

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    • 4.3 64-Bit SCRIPTS Selectors

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    • 4.4 Phase Mismatch Jump Registers

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  • Chapter5 SCSI SCRIPTS Instruction Set

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    • 5.1 Low Level Register Interface Mode

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    • 5.2 High Level SCSI SCRIPTS Mode

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      • Table 5.1 SCRIPTS Instructions

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      • 5.2.1 Sample Operation

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        • Figure5.1 SCRIPTS Overview

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    • 5.3 Block Move Instruction

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      • 5.3.1 First Dword

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        • Table 5.2 SCSI Information Transfer Phase

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      • 5.3.2 Second Dword

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    • 5.4 I/O Instruction

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      • 5.4.1 First Dword

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      • 5.4.2 Second Dword

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    • 5.5 Read/Write Instructions

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      • 5.5.1 First Dword

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      • 5.5.2 Second Dword

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      • 5.5.3 Read-Modify-Write Cycles

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      • 5.5.4 Move To/From SFBR Cycles

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        • Table 5.3 Read/Write Instructions

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    • 5.6 Transfer Control Instructions

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      • 5.6.1 First Dword

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        • Table 5.4 Transfer Control Instructions

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        • Table 5.5 SCSI Phase Comparisons

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      • 5.6.2 Second Dword

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    • 5.7 Memory Move Instructions

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      • 5.7.1 First Dword

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      • 5.7.2 Read/Write System Memory from SCRIPTS

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      • 5.7.3 Second Dword

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      • 5.7.4 Third Dword

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    • 5.8 Load and Store Instructions

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      • 5.8.1 First Dword

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      • 5.8.2 Second Dword

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  • Chapter6 Electrical Specifications

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    • 6.1 DC Characteristics

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      • Table 6.1 Absolute Maximum Stress Ratings

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      • Table 6.2 Operating Conditions

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      • Table 6.3 Input Capacitance

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      • Table 6.4 Bidirectional Signals—MAD[7:0], MAS/[1:0], MCE/, MOE/, MWE/

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      • Table 6.5 Bidirectional Signals—GPIO0_FETCH/, GPIO1_MASTER/, GPIO[2:4]

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      • Table 6.6 Bidirectional Signals—AD[31:0], C_BE[3:0]/, FRAME/, IRDY/, TRDY/, DEVSEL/, STOP/, PERR/...

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      • Table 6.7 Input Signals—CLK, GNT/, IDSEL, RST/, SCLK, TCK, TDI, TEST_HSC, TEST_RST, TMS, TRST/

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      • Table 6.8 Output Signal—TDO

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      • Table 6.9 Output Signals—IRQ/, MAC/_TESTOUT, REQ/

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      • Table 6.10 Output Signal—SERR/

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    • 6.2 TolerANT Technology Electrical Characteristics

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      • Table 6.11 TolerANT Technology Electrical Characteristics for SE SCSI Signals

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      • Figure6.1 Rise and Fall Time Test Condition

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      • Figure6.2 SCSI Input Filtering

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      • Figure6.3 Hysteresis of SCSI Receivers

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      • Figure6.4 Input Current as a Function of Input Voltage

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      • Figure6.5 Output Current as a Function of Output Voltage

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    • 6.3 AC Characteristics

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      • Table 6.12 External Clock

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      • Figure6.6 External Clock

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      • Table 6.13 Reset Input

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      • Figure6.7 Reset Input

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      • Table 6.14 Interrupt Output

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      • Figure6.8 Interrupt Output

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    • 6.4 PCI and External Memory Interface Timing Diagrams

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      • 6.4.1 Target Timing

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        • Table 6.15 PCI Configuration Register Read

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        • Figure6.9 PCI Configuration Register Read

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        • Table 6.16 PCI Configuration Register Write

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        • Figure6.10 PCI Configuration Register Write

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        • Table 6.17 32-Bit Operating Register/SCRIPTS RAM Read

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        • Figure6.11 32-Bit Operating Register/SCRIPTS RAM Read

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        • Table 6.18 64-Bit Address Operating Register/SCRIPTS RAM Read

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        • Figure6.12 64-Bit Address Operating Register/SCRIPTS RAM Read

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        • Table 6.19 32-Bit Operating Register/SCRIPTS RAM Write

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        • Figure6.13 32-Bit Operating Register/SCRIPTS RAM Write

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        • Table 6.20 64-Bit Address Operating Register/SCRIPTS RAM Write

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        • Figure6.14 64-Bit Address Operating Register/SCRIPTS RAM Write

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      • 6.4.2 Initiator Timing

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        • Table 6.21 Nonburst Opcode Fetch, 32-Bit Address and Data

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        • Figure6.15 Nonburst Opcode Fetch, 32-Bit Address and Data

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        • Table 6.22 Burst Opcode Fetch, 32-Bit Address and Data

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        • Figure6.16 Burst Opcode Fetch, 32-Bit Address and Data

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        • Table 6.23 Back-to-Back Read, 32-Bit Address and Data

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        • Figure6.17 Back-to-Back Read, 32-Bit Address and Data

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        • Table 6.24 Back-to-Back Write, 32-Bit Address and Data

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        • Figure6.18 Back-to-Back Write, 32-Bit Address and Data

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        • Table 6.25 Burst Read, 32-Bit Address and Data

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        • Figure6.19 Burst Read, 32-Bit Address and Data

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        • Table 6.26 Burst Read, 64-Bit Address and Data

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        • Figure6.20 Burst Read, 64-Bit Address and Data

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        • Table 6.27 Burst Write, 32-Bit Address and Data

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        • Figure6.21 Burst Write, 32-Bit Address and Data

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        • Table 6.28 Burst Write, 64-Bit Address and 32-Bit Data

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        • Figure6.22 Burst Write, 64-Bit Address and 32-Bit Data

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      • 6.4.3 External Memory Timing

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        • Table 6.29 External Memory Read

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        • Figure6.23 External Memory Read

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        • Table 6.30 External Memory Write

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        • Figure6.24 External Memory Write

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        • Table 6.31 Normal/Fast Memory (³ 128 Kbytes) Single Byte Access Read Cycle

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        • Figure6.25 Normal/Fast Memory (³ 128 Kbytes) Single Byte Access Read Cycle

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        • Table 6.32 Normal/Fast Memory (³ 128 Kbytes) Single Byte Access Write Cycle

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        • Figure6.26 Normal/Fast Memory (³ 128 Kbytes) Single Byte Access Write Cycle

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        • Figure6.27 Normal/Fast Memory (³ 128 Kbytes) Multiple Byte Access Read Cycle

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        • Figure6.28 Normal/Fast Memory (³ 128 Kbytes) Multiple Byte Access Write Cycle

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        • Table 6.33 Slow Memory (£ 128 Kbytes) Read Cycle

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        • Figure6.29 Slow Memory (£ 128 Kbytes) Read Cycle

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        • Table 6.34 Slow Memory (£ 128 Kbytes) Write Cycle

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        • Figure6.30 Slow Memory (£ 128 Kbytes) Write Cycle

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        • Table 6.35 £ 64 Kbytes ROM Read Cycle

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        • Figure6.31 £ 64 Kbytes ROM Read Cycle

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        • Table 6.36 £ 64 Kbyte ROM Write Cycle

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        • Figure6.32 £ 64 Kbyte ROM Write Cycle

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    • 6.5 SCSI Timing Diagrams

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      • Table 6.37 Initiator Asynchronous Send

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      • Figure6.33 Initiator Asynchronous Send

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      • Table 6.38 Initiator Asynchronous Receive

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      • Figure6.34 Initiator Asynchronous Receive

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      • Table 6.39 Target Asynchronous Send

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      • Figure6.35 Target Asynchronous Send

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      • Table 6.40 Target Asynchronous Receive

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      • Figure6.36 Target Asynchronous Receive

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      • Table 6.41 SCSI-1 Transfers (5.0 Mbytes)

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      • Table 6.42 SCSI-2 Fast Transfers 10.0 Mbytes (8-Bit Transfers) or 20.0 Mbytes (16-Bit Transfers) ...

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      • Table 6.43 Ultra SCSI Transfers 20.0 Mbytes (8-Bit Transfers) or 40.0 Mbytes (16-Bit Transfers) Q...

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      • Figure6.37 Initiator and Target Synchronous Transfer

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    • 6.6 Package Diagrams

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      • Figure6.38 LSI53C875A 160-Pin PQFP Mechanical Drawing

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      • Table6.44 160 PQFP Pin List by Location

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      • Figure6.39 169-Pin BGA Mechanical Drawing

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      • Table6.45 169 BGA Pin List by Location

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  • AppendixA Register Summary

    301
    • TableA.1 LSI53C875A PCI Register Map

      301
    • TableA.2 LSI53C875A SCSI Register Map

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  • AppendixB External Memory Interface Diagram Examples

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    • FigureB.1 16 Kbyte Interface with 200 ns Memory

      307
    • FigureB.2 64 Kbyte Interface with 150 ns Memory

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    • FigureB.3 128 Kbytes, 256 Kbytes, 512 Kbytes, or 1 Mbyte Interface with 150 ns Memory

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    • FigureB.4 512 Kbyte Interface with 150 ns Memory

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  • Index

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  • Customer Feedback

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