Manuali utente per Microchip Technology AC164336

Sommario

• High-Performance Modified RISC CPU:

  1
• DSP Engine Features:

  1
• Peripheral Features:

  1
• Power Supply PWM Module Features:

  1
• Analog Features:

  2
• Special Microcontroller Features:

  2
• CMOS Technology:

  2
• Pin Diagrams

  3
• Table of Contents

  7
• Most Current Data Sheet

  8
• Errata

  8
• Customer Notification System

  8
• 1.0 Device Overview

  9
  • FIGURE 1-1: dsPIC30F1010 Block Diagram

    10
  • TABLE 1-1: PINOUT I/O Descriptions for dsPIC30F1010

    11
  • FIGURE 1-2: dspic30f2020 block diagram

    13
  • TABLE 1-2: PINOUT I/O Descriptions for dsPIC30F2020

    14
  • FIGURE 1-3: dsPIC30F2023 Block Diagram

    16
  • TABLE 1-3: PINOUT I/O Descriptions for dsPIC30F2023

    17
• 2.0 CPU Architecture Overview

  19
  • 2.1 Core Overview

    19
  • 2.2 Programmer’s Model

    20
    • 2.2.1 Software Stack Pointer/ FRAMe pointer

      20
    • 2.2.2 Status Register

      20
    • 2.2.3 program counter

      20
      • FIGURE 2-1: Programmer’s Model

        21
  • 2.3 Divide Support

    22
    • TABLE 2-1: Divide Instructions

      22
  • 2.4 DSP Engine

    23
    • TABLE 2-2: DSP Instruction Summary

      23
    • FIGURE 2-2: DSP ENGINE BLOCK DIAGRAM

      24
    • 2.4.1 Multiplier

      25
    • 2.4.2 Data Accumulators and Adder/Subtracter

      25
    • 2.4.3 Barrel Shifter

      27
• 3.0 Memory Organization

  29
  • 3.1 Program Address Space

    29
    • FIGURE 3-1: program Space memory map FOR dsPIC30F1010/202X

      29
    • TABLE 3-1: Program Space Address Construction

      30
    • FIGURE 3-2: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION

      30
    • 3.1.1 Data Access From Program Memory using Table Instructions

      31
      • FIGURE 3-3: Program Data Table Access (Least Significant Word)

        31
      • FIGURE 3-4: Program Data Table Access (Most Significant Byte)

        32
    • 3.1.2 Data Access from Program Memory Using Program Space Visibility

      32
      • FIGURE 3-5: Data Space Window Into Program Space Operation

        33
  • 3.2 Data Address Space

    33
    • 3.2.1 Data Space Memory Map

      33
      • FIGURE 3-6: DATA SPACE MEMORY MAP

        34
      • FIGURE 3-7: DATA SPACE FOR MCU AND DSP (MAC CLASS) INSTRUCTIONS

        35
    • 3.2.2 Data Spaces

      36
      • TABLE 3-2: Effect of Invalid Memory Accesses

        36
    • 3.2.3 Data Space Width

      36
    • 3.2.4 Data Alignment

      36
      • FIGURE 3-8: DATA ALIGNMENT

        36
    • 3.2.5 Near Data Space

      37
    • 3.2.6 Software Stack

      37
      • FIGURE 3-9: CALL Stack FRAME

        37
    • 3.2.7 Data RAM Protection

      37
      • TABLE 3-3: Core Register Map

        38
• 4.0 Address Generator Units

  41
  • 4.1 Instruction Addressing Modes

    41
    • 4.1.1 file register instructions

      41
      • TABLE 4-1: Fundamental Addressing Modes Supported

        41
    • 4.1.2 mcu instructions

      42
    • 4.1.3 Move and accumulator instructions

      42
    • 4.1.4 Mac instructions

      42
    • 4.1.5 other instructions

      42
  • 4.2 Modulo Addressing

    43
    • 4.2.1 Start and End Address

      43
    • 4.2.2 W Address Register Selection

      43
      • FIGURE 4-1: MODULO ADDRESSING OPERATION EXAMPLE

        44
    • 4.2.3 Modulo Addressing Applicability

      45
  • 4.3 Bit-Reversed Addressing

    45
    • 4.3.1 Bit-Reversed Addressing Implementation

      45
      • FIGURE 4-2: BIT-REVERSED ADDRESS EXAMPLE

        45
      • TABLE 4-2: BiT-Reversed Address Sequence (16-entry)

        46
      • TABLE 4-3: Bit-Reversed Address Modifier Values For XBREV Register

        46
• 5.0 Interrupts

  47
  • 5.1 Interrupt Priority

    48
    • TABLE 5-1: dsPIC30F1010/202X Interrupt Vector Table

      48
  • 5.2 Reset Sequence

    49
    • 5.2.1 Reset Sources

      49
  • 5.3 Traps

    49
    • 5.3.1 Trap Sources

      49
    • 5.3.2 Hard and Soft Traps

      50
      • FIGURE 5-1: Trap Vectors

        50
  • 5.4 Interrupt Sequence

    51
    • FIGURE 5-2: INTERRUPT STACK FRAME

      51
  • 5.5 Alternate Vector Table

    51
  • 5.6 Fast Context Saving

    51
  • 5.7 External Interrupt Requests

    51
  • 5.8 Wake-up from Sleep and Idle

    51
    • Register 5-1: IntCON1: Interrupt Control Register 1

      52
    • Register 5-2: INTCON2: Interrupt Control REgister 2

      54
    • Register 5-3: IFs0: Interrupt Flag Status Register 0

      55
    • Register 5-4: IFS1: Interrupt Flag STatus Register 1

      57
    • Register 5-5: IFS2: Interrupt Flag Status Register 2

      58
    • Register 5-6: IEC0: Interrupt Enable Control Register 0

      59
    • Register 5-7: IEC1: Interrupt Enable Control Register 1

      61
    • Register 5-8: IEC2: Interrupt Enable Control Register 2

      62
    • Register 5-9: IPC0: Interrupt Priority Control Register 0

      63
    • Register 5-10: IPC1: Interrupt Priority Control Register 1

      64
    • Register 5-11: IPC2: Interrupt Priority Control Register 2

      65
    • Register 5-12: IPC3: Interrupt Priority Control Register 3

      66
    • Register 5-13: IPC4: Interrupt Priority Control Register 4

      67
    • Register 5-14: IPC5: Interrupt Priority Control Register 5

      68
    • Register 5-15: IPC6: Interrupt Priority Control Register 6

      69
    • Register 5-16: IPC7: Interrupt Priority Control Register 7

      70
    • Register 5-17: IPC8: Interrupt Priority Control Register 8

      71
    • Register 5-18: IPC9: Interrupt Priority Control Register 9

      72
    • Register 5-19: IPC10: Interrupt Priority Control Register 10

      73
    • Register 5-20: INTTREG: INTERRUPT CONTROL AND STATUS REGISTER

      74
    • TABLE 5-2: Interrupt Controller Register Map

      75
• 6.0 I/O Ports

  77
  • 6.1 Parallel I/O (PIO) Ports

    77
    • FIGURE 6-1: Block Diagram of a ShAred PORT Structure

      77
  • 6.2 Configuring Analog Port Pins

    78
    • 6.2.1 I/O Port Write/Read Timing

      78
      • EXAMPLE 6-1: Port Write/Read Example

        78
  • 6.3 Input Change Notification

    78
    • TABLE 6-1: dsPIC30F1010/2020 Port Register Map

      79
    • TABLE 6-2: dsPIC30F2023 Port Register MAp

      80
    • TABLE 6-3: dsPIC30F1010/202x INPUT CHANGE NOTIFICATION REGISTER MAP

      80
• 7.0 Flash Program Memory

  81
  • 7.1 In-Circuit Serial Programming (ICSP)

    81
  • 7.2 Run-Time Self-Programming (RTSP)

    81
  • 7.3 Table Instruction Operation Summary

    81
    • FIGURE 7-1: ADDRESSING FOR TABLE AND NVM REGISTERS

      81
  • 7.4 RTSP Operation

    82
  • 7.5 Control Registers

    82
    • 7.5.1 NVMCON Register

      82
    • 7.5.2 NVMADR Register

      82
    • 7.5.3 NVMADRU Register

      82
    • 7.5.4 NVMKEY Register

      82
  • 7.6 Programming Operations

    83
    • 7.6.1 Programming Algorithm for Program Flash

      83
    • 7.6.2 Erasing a Row of Program Memory

      83
      • EXAMPLE 7-1: erasing A row of PROGRAM memory

        83
    • 7.6.3 Loading Write Latches

      84
      • EXAMPLE 7-2: loading write latches

        84
    • 7.6.4 Initiating The Programming Sequence

      84
      • EXAMPLE 7-3: initiating a programming sequence

        84
      • TABLE 7-1: NVM Register Map

        85
• 8.0 Timer1 Module

  87
  • FIGURE 8-1: 16-bit Timer1 Module Block diagram (Type A Timer)

    88
  • 8.1 Timer Gate Operation

    88
  • 8.2 Timer Prescaler

    88
  • 8.3 Timer Operation During Sleep Mode

    88
  • 8.4 Timer Interrupt

    88
    • TABLE 8-1: Timer1 Register Map

      89
• 9.0 Timer2/3 Module

  91
  • FIGURE 9-1: 32-bit TIMER2/3 BLOCK DIAGRAM

    92
  • FIGURE 9-2: 16-bit TIMER2 BLOCK DIAGRAM

    93
  • FIGURE 9-3: 16-bit TIMER3 BLOCK DIAGRAM

    93
  • 9.1 Timer Gate Operation

    94
  • 9.2 ADC Event Trigger

    94
  • 9.3 Timer Prescaler

    94
  • 9.4 Timer Operation During Sleep Mode

    94
  • 9.5 Timer Interrupt

    94
    • TABLE 9-1: Timer2/3 register map

      95
• 10.0 Input Capture Module

  97
  • FIGURE 10-1: Input Capture Mode Block Diagram

    97
  • 10.1 Simple Capture Event Mode

    98
    • 10.1.1 Capture Prescaler

      98
    • 10.1.2 Capture Buffer Operation

      98
    • 10.1.3 Timer2 and Timer3 selection mode

      98
    • 10.1.4 Hall Sensor Mode

      98
  • 10.2 Input Capture Operation During Sleep and Idle Modes

    99
    • 10.2.1 Input Capture in CPU Sleep Mode

      99
    • 10.2.2 Input Capture in CPU Idle Mode

      99
  • 10.3 Input Capture Interrupts

    99
    • TABLE 10-1: Input Capture Register Map

      100
• 11.0 Output Compare Module

  101
  • FIGURE 11-1: Output Compare Mode Block Diagram

    101
  • 11.1 Timer2 and Timer3 Selection Mode

    102
  • 11.2 Simple Output Compare Match Mode

    102
  • 11.3 Dual Output Compare Match Mode

    102
    • 11.3.1 Single Pulse Mode

      102
    • 11.3.2 Continuous Pulse Mode

      102
  • 11.4 Simple PWM Mode

    102
    • 11.4.1 PWM Period

      103
      • EQUATION 11-1: PWM Period

        103
    • 11.4.2 PWM with FAULt protection Input pin

      103
  • 11.5 Output Compare Operation During CPU Sleep Mode

    103
  • 11.6 Output Compare Operation During CPU Idle Mode

    103
    • FIGURE 11-1: PWM output Timing

      104
  • 11.7 Output Compare Interrupts

    104
    • TABLE 11-1: Output Compare Register Map

      105
• 12.0 Power Supply PWM

  107
  • 12.1 Features Overview

    107
  • 12.2 Description

    107
    • FIGURE 12-1: Simplified Conceptual Block Diagram of Power Supply PWM

      108
    • FIGURE 12-2: Partitioned output Pair, complementary PWM Mode

      109
  • 12.3 Control Registers

    109
    • Register 12-1: PTCON: PWM Time Base Control Register

      110
    • Register 12-2: PTPER: Primary Time Base Register

      111
    • Register 12-3: SEVTCMP: PWM Special Event Compare Register

      111
    • Register 12-4: MDC: PWM Master Duty Cycle Register

      112
    • Register 12-5: PWMCONx: PWM Control Register

      112
    • Register 12-6: PDCx: PWM Generator Duty Cycle Register

      113
    • Register 12-7: PHASEx: PWM Phase-Shift Register

      114
    • Register 12-8: DTRx: PWM Dead-Time Register

      114
    • Register 12-9: ALTDTRx: PWM Alternate Dead-Time Register

      115
    • Register 12-10: TRGCONx: PWM TRIGGER Control Register

      115
    • Register 12-11: IOCONx: PWM I/O Control Register

      116
    • Register 12-12: FCLCONx: PWM Fault Current-Limit Control Register

      117
    • Register 12-13: TRIGx: PWM Trigger Compare Value Register

      119
    • Register 12-14: LEBCONx: Leading Edge Blanking Control Register

      120
  • 12.4 Module Functionality

    121
    • 12.4.1 Standard Edge-Aligned PWM Mode

      121
      • FIGURE 12-3: Edge-Aligned PWM

        121
    • 12.4.2 Complementary PWM Mode

      121
      • FIGURE 12-4: Complementary PWM

        121
    • 12.4.3 Push-Pull PWM Mode

      121
      • FIGURE 12-5: Push-Pull PWM

        121
    • 12.4.4 Multi-Phase PWM Mode

      122
      • FIGURE 12-6: Multi-Phase PWM

        122
    • 12.4.5 Variable Phase PWM Mode

      122
      • FIGURE 12-7: Variable Phase PWM

        122
    • 12.4.6 Current-Limit PWM Mode

      122
      • FIGURE 12-8: Cycle-by-Cycle Current-LIMIT PWM Mode

        122
    • 12.4.7 Constant Off-Time PWM

      123
      • FIGURE 12-9: Constant Off-Time PWM

        123
    • 12.4.8 Current Reset PWM Mode

      123
      • FIGURE 12-10: Current Reset PWM

        123
    • 12.4.9 Independent Time Base PWM

      123
      • FIGURE 12-11: Independent Time base PWM

        123
  • 12.5 Primary PWM Time Base

    124
    • FIGURE 12-12: PTMR Block Diagram

      124
    • 12.5.1 PTMR Synchronization

      124
  • 12.6 Primary PWM Time Base Roll Counter

    124
  • 12.7 Individual PWM Time Base(s)

    124
    • FIGURE 12-13: TMRx Block Diagram

      125
  • 12.8 PWM Period

    125
  • 12.9 PWM Frequency and Duty Cycle Resolution

    125
    • TABLE 12-1: Available Pwm frequencies and resolutions @ 30 MIPS

      125
    • TABLE 12-2: Available Pwm frequencies and resolutions @ 20 MIPS

      125
  • 12.10 PWM Duty Cycle Comparison Units

    126
    • FIGURE 12-14: Duty Cycle Comparison

      126
  • 12.11 Complementary PWM Outputs

    126
  • 12.12 Independent PWM Outputs

    126
  • 12.13 Duty Cycle Limits

    126
  • 12.14 Dead-Time Generation

    127
    • FIGURE 12-15: Dead-Time Insertion for Complementary PWM

      127
    • FIGURE 12-16: Dead-time Control Units block diagram

      127
    • 12.14.1 DEAD-TIME GENERATORS

      127
    • 12.14.2 Alternate Dead-Time Source

      127
      • FIGURE 12-17: DUal dead-time waveforms

        128
    • 12.14.3 Dead-Time ranges

      128
      • TABLE 12-3: Example Dead-Time Ranges

        128
    • 12.14.4 Dead-Time Insertion Timing

      128
    • 12.14.5 Dead-Time distortion

      128
      • FIGURE 12-18: Dead-Time insertion (PWM OUTPUT SIGNAL TIMING MAY BE DELAYED)

        128
  • 12.15 Configuring a PWM Channel

    129
  • 12.16 Speed Limits of PWM Output Circuitry

    129
  • 12.17 PWM Special Event Trigger

    129
    • 12.17.1 Special Event Trigger Enable

      129
    • 12.17.2 Special Event Trigger postscaler

      129
  • 12.18 Individual PWM Triggers

    129
    • EXAMPLE 12-1: Code Example for Configuring PWM Channel 1

      130
    • FIGURE 12-19: PWM Trigger Block Diagram

      131
  • 12.19 PWM Interrupts

    131
  • 12.20 PWM Time Base Interrupts

    131
  • 12.21 PWM Fault and Current-Limit Pins

    131
  • 12.22 Leading Edge Blanking

    131
  • 12.23 PWM Fault Pins

    132
    • FIGURE 12-20: PWM Fault Control Logic Diagram

      132
    • 12.23.1 Fault Interrupts

      133
    • 12.23.2 Fault states

      133
    • 12.23.3 Fault input modes

      133
    • 12.23.4 Fault ENTRY

      133
    • 12.23.5 Fault EXIT

      133
    • 12.23.6 Fault exit with PTMR disabled

      133
    • 12.23.7 Fault Pin Software Control

      133
  • 12.24 PWM Current-Limit Pins

    134
    • 12.24.1 Current-Limit Interrupts

      134
      • FIGURE 12-21: PWM Current-Limit Control Logic Diagram

        134
  • 12.25 Simultaneous PWM Faults and Current Limits

    135
  • 12.26 PWM Fault and Current-Limit TRG Outputs To ADC

    135
  • 12.27 PWM Output Override Priority

    135
  • 12.28 Fault and Current-Limit Override Issues with Dead-Time Logic

    135
  • 12.29 Asserting Outputs via Current Limit

    135
  • 12.30 PWM Immediate Update

    135
  • 12.31 PWM Output Override

    135
    • 12.31.1 complementary output mode

      135
    • 12.31.2 override synchronization

      136
  • 12.32 Functional Exceptions

    136
    • 12.32.1 Power Reset Conditions

      136
    • 12.32.2 SLEEP Mode

      136
    • 12.32.3 CPU IDLE Mode

      136
  • 12.33 Register Bit Alignment

    136
  • 12.34 Application Examples:

    137
    • 12.34.1 Standard PWM Mode

      137
      • FIGURE 12-22: Applications of Standard PWM Mode

        137
    • 12.34.2 Application of Complementary PWM Mode

      137
      • FIGURE 12-23: Applications of Complementary PWM mode

        137
    • 12.34.3 Application of Push-Pull PWM Mode

      138
      • FIGURE 12-24: Applications of Push- Pull Pwm Mode

        138
    • 12.34.4 Application of Multi-Phase PWM Mode

      138
      • FIGURE 12-25: Applications of Multi- Phase Pwm Mode

        138
    • 12.34.5 Application of Variable Phase PWM Mode

      139
      • FIGURE 12-26: Application of Variable Phase PWM mode

        139
    • 12.34.6 Application of Current Reset PWM Mode

      139
      • FIGURE 12-27: Application of Current Reset PWM mode

        139
  • 12.35 Methods to reduce EMI

    140
    • 12.35.1 Method #1: programmable FRC dither

      140
    • 12.35.2 Method #2: Software Controlled Dither

      140
    • 12.35.3 Method #3: Software Scaling of Time Base Period

      140
    • 12.35.4 Method #4: Frequency Modulation

      140
    • 12.35.5 INDEPENDENT PWM CHANNEL DITHERING ISSUES:

      140
  • 12.36 External Synchronization Features

    141
  • 12.37 CPU Load Staggering

    141
  • 12.38 External Trigger Blanking

    141
    • TABLE 12-4: Power Supply PWM Register Map

      142
• 13.0 Serial Peripheral Interface (SPI)

  145
  • FIGURE 13-1: SPI Module Block Diagram

    146
  • FIGURE 13-2: SPI Master/Slave Connection

    147
  • FIGURE 13-3: SPI Master, Frame Master Connection Diagram

    147
  • FIGURE 13-4: SPI Master, Frame Slave Connection Diagram

    147
  • FIGURE 13-5: SPI Slave, Frame Master Connection Diagram

    148
  • FIGURE 13-6: SPI Slave, Frame Slave Connection Diagram

    148
  • EQUATION 13-1: Relationship Between Device and SPI Clock Speed

    148
  • TABLE 13-1: Sample SCKx Frequencies

    148
  • Register 13-1: SPIxSTAT: SPIx Status and Control Register

    149
  • Register 13-2: SPIxCON1: SPIx Control Register 1

    150
  • Register 13-3: SPIxCON2: SPIx Control Register 2

    151
  • TABLE 13-2: SPI1 Register Map

    152
• 14.0 I2C™ Module

  153
  • 14.1 Operating Function Description

    153
    • 14.1.1 VARIOUS I2C MODES

      153
    • 14.1.2 Pin Configuration In I2C Mode

      153
      • FIGURE 14-1: Programmer’s model

        153
    • 14.1.3 I2C Registers

      153
      • FIGURE 14-2: I2C™ BLOCK DIAGRAM

        154
  • 14.2 I2C Module Addresses

    155
  • 14.3 I2C 7-bit Slave Mode Operation

    155
    • 14.3.1 Slave Transmission

      155
    • 14.3.2 Slave Reception

      155
  • 14.4 I2C 10-bit Slave Mode Operation

    155
    • 14.4.1 10-bit Mode Slave Transmission

      155
    • 14.4.2 10-bit Mode Slave Reception

      155
  • 14.5 Automatic Clock Stretch

    156
    • 14.5.1 transmit Clock Stretching

      156
    • 14.5.2 RECEIVE CLOCK STRETCHING

      156
    • 14.5.3 Clock Stretching During 7-bit Addressing (STREN = 1)

      156
    • 14.5.4 Clock Stretching During 10-bit Addressing (STREN = 1)

      156
  • 14.6 Software Controlled Clock Stretching (STREN = 1)

    156
  • 14.7 Interrupts

    156
  • 14.8 Slope Control

    157
  • 14.9 IPMI Support

    157
  • 14.10 General Call Address Support

    157
  • 14.11 I2C Master Support

    157
  • 14.12 I2C Master Operation

    157
    • 14.12.1 I2C Master Transmission

      157
    • 14.12.2 I2C Master Reception

      157
    • 14.12.3 Baud Rate Generator

      158
    • 14.12.4 Clock Arbitration

      158
    • 14.12.5 Multi-Master Communication, Bus Collision And Bus Arbitration

      158
  • 14.13 I2C Module Operation During CPU Sleep and Idle Modes

    158
    • 14.13.1 I2C Operation During CPU Sleep MoDE

      158
    • 14.13.2 I2C Operation During CPU Idle Mode

      158
      • TABLE 14-1: I2C™ Register Map

        159
• 15.0 Universal Asynchronous Receiver Transmitter (UART) Module

  161
  • FIGURE 15-1: UART Simplified Block Diagram

    161
  • 15.1 UART Baud Rate Generator (BRG)

    162
    • EQUATION 15-1: UART Baud Rate with BRGH = 0(1,2,3)

      162
    • EQUATION 15-2: UART Baud Rate with BRGH = 1(1,2,3)

      162
    • EXAMPLE 15-1: Baud Rate Error Calculation (BRGH = 0)(1)

      162
  • 15.2 Transmitting in 8-bit Data Mode

    163
  • 15.3 Transmitting in 9-bit Data Mode

    163
  • 15.4 Break and Sync Transmit Sequence

    163
  • 15.5 Receiving in 8-bit or 9-bit Data Mode

    163
  • 15.6 Built-in IrDA Encoder and Decoder

    163
  • 15.7 Alternate UART I/O Pins

    163
    • Register 15-1: U1MODE: UART1 MODE Register

      164
    • Register 15-2: U1STA: UART1 Status and Control Register

      166
    • TABLE 15-1: UART1 Register Map

      168
• 16.0 10-bit 2 Msps Analog-to- Digital Converter (ADC) Module

  169
  • 16.1 Features

    169
  • 16.2 Description

    169
  • 16.3 Module Functionality

    169
    • FIGURE 16-1: ADC Block Diagram

      170
    • Register 16-1: A/D Control Register (ADCON)

      171
    • Register 16-2: A/D Status Register (ADSTAT)

      173
    • Register 16-3: A/D Base Register (ADBASE)

      174
    • Register 16-4: A/D Port Configuration Register (ADPCFG)

      174
    • Register 16-5: A/D Convert Pair Control Register 0 (ADCPC0)

      175
    • Register 16-6: A/D Convert Pair Control Register 1 (ADCPC1)

      177
    • Register 16-7: A/D Convert Pair Control Register 2 (ADCPC2)

      179
  • 16.4 ADC Result Buffer

    181
  • 16.5 Application Information

    181
    • FIGURE 16-2: Application Example: Importance of Precise Sampling

      181
  • 16.6 Reverse Conversion Order

    182
  • 16.7 Simultaneous and Sequential Sampling in a pair

    182
  • 16.8 Group Interrupt Generation

    182
  • 16.9 Individual Pair Interrupts

    183
  • 16.10 Early Interrupt Generation

    183
  • 16.11 Conflict Resolution

    183
  • 16.12 Deliberate Conflicts

    183
  • 16.13 ADC Clock Selection

    183
  • 16.14 ADC Base Register

    183
    • EXAMPLE 16-1: ADC Base Register Code

      184
    • EXAMPLE 16-1: ADC Base Register Code (Continued)

      185
  • 16.15 Changing A/D Clock

    185
  • 16.16 Sample and Conversion

    185
  • 16.17 A/D Sample and Convert Timing

    186
    • FIGURE 16-3: Detailed Conversion sequence timings, SEQSAMP = 0, not busy

      186
    • FIGURE 16-4: Detailed Conversion sequence timings, SEQSAMP = 1

      187
  • 16.18 Module Power-Down Modes

    188
  • 16.19 Effects of a Reset

    188
  • 16.20 Configuring Analog Port Pins

    188
  • 16.21 Output Formats

    188
    • FIGURE 16-5: A/D Output Data Format

      189
    • TABLE 16-1: ADC Register Map

      190
• 17.0 SMPS Comparator Module

  191
  • 17.1 Features Overview

    191
    • FIGURE 17-1: Comparator Module Block Diagram

      191
  • 17.2 Module Applications

    191
  • 17.3 Module Description

    192
  • 17.4 DAC

    192
  • 17.5 Interaction with I/O Buffers

    192
  • 17.6 Digital Logic

    192
  • 17.7 Comparator Input Range

    192
  • 17.8 DAC Output Range

    192
  • 17.9 Comparator Registers

    192
    • Register 17-1: Comparator Control Registerx (CMPCONx)

      193
    • Register 17-2: Comparator DAC Control Registerx (CMPDACx)

      194
    • TABLE 17-1: Analog ComparAtor Control Register Map

      195
• 18.0 System Integration

  197
  • 18.1 Oscillator System Overview

    197
  • 18.2 Oscillator Control Registers

    197
    • FIGURE 18-1: OSCILLATOR SYSTEM BLOCK DIAGRAM

      198
    • Register 18-1: OSCCON: Oscillator Control Register

      199
    • Register 18-2: OSCTUN: Oscillator TUNING Register

      201
    • Register 18-3: OSCTUN2: Oscillator Tuning Register 2

      202
    • Register 18-4: LFSR: Linear Feedback Shift Register

      202
    • Register 18-5: FOSCSEL: Oscillator Selection Configuration Bits

      203
    • Register 18-6: FOSC: Oscillator Selection Configuration Bits

      204
    • 18.2.1 accidental write Protection

      205
  • 18.3 Oscillator Configurations

    205
    • FIGURE 18-2: System Clock and Fadc Derivation

      205
    • 18.3.1 Initial Clock source selection

      206
      • TABLE 18-1: Configuration Bit Values for Clock Selection

        206
    • 18.3.2 Oscillator Start-up Timer (OST)

      206
    • 18.3.3 Phase Locked Loop (PLL)

      206
      • TABLE 18-2: PLL frequency range

        206
  • 18.4 PRIMARY oscillator on OSC1/ OSC2 pins:

    207
    • FIGURE 18-3: Primary oscillator

      207
  • 18.5 External Clock Input

    207
    • FIGURE 18-4: External Clock Input Operation (EC oscillator Configuration)

      207
    • FIGURE 18-5: External Clock Input Operation (ECIO oscillator Configuration)

      207
  • 18.6 Internal Fast RC oscillator (FRC)

    208
    • 18.6.1 Frequency Range Selection

      208
    • 18.6.2 Nominal Frequency Values

      208
    • 18.6.3 FRC Frequency USER TUNING

      208
    • 18.6.4 Clock dithering logic

      208
    • 18.6.5 frequency sequencing mode

      208
    • 18.6.6 Pseudo random clock dithering mode

      208
    • 18.6.7 Fail-Safe Clock Monitor

      208
  • 18.7 Reset

    209
    • FIGURE 18-6: FRC TUNE Dither Logic Block Diagram

      210
    • FIGURE 18-7: Reset SYSTEM BLOCK DIAGRAM

      210
    • 18.7.1 POR: Power-ON reset

      211
      • FIGURE 18-8: Time-out Sequence on Power-up (MCLR Tied to Vdd)

        211
      • FIGURE 18-9: Time-out Sequence on Power-up (MCLR not Tied to Vdd): Case 1

        211
      • FIGURE 18-10: Time-out Sequence on Power-up (MCLR not Tied to Vdd): Case 2

        212
      • FIGURE 18-11: External Power-on Reset Circuit (for Slow Vdd Power-up)

        212
      • TABLE 18-3: Initialization Condition for RCON RegisteR CASE 1

        213
      • TABLE 18-4: Initialization Condition for RCON RegisteR CASE 2

        213
  • 18.8 Watchdog Timer (WDT)

    214
    • 18.8.1 Watchdog Timer Operation

      214
    • 18.8.2 Enabling and Disabling the WDT

      214
  • 18.9 Power-Saving Modes

    214
    • 18.9.1 Sleep Mode

      214
    • 18.9.2 Idle Mode

      215
  • 18.10 Device Configuration Registers

    215
    • TABLE 18-5: FGS and FBS Bit descriptions for the dsPIC30F1010

      216
    • TABLE 18-6: FGS and FBS Bit Descriptions for the dsPIC30F202x

      216
    • TABLE 18-7: FWDT and FPOR bit descriptions for dsPIC30F1010/202X

      217
  • 18.11 In-Circuit Debugger

    217
    • TABLE 18-8: System Integration Register Map For dsPIC30F202x

      218
    • TABLE 18-9: DEVICE Configuration Register Map

      218
• 19.0 Instruction Set Summary

  219
  • TABLE 19-1: Symbols used in Opcode Descriptions

    220
  • TABLE 19-2: Instruction Set OVERVIEW

    222
• 20.0 Development Support

  227
  • 20.1 MPLAB X Integrated Development Environment Software

    227
  • 20.2 MPLAB XC Compilers

    228
  • 20.3 MPASM Assembler

    228
  • 20.4 MPLINK Object Linker/ MPLIB Object Librarian

    228
  • 20.5 MPLAB Assembler, Linker and Librarian for Various Device Families

    228
  • 20.6 MPLAB X SIM Software Simulator

    229
  • 20.7 MPLAB REAL ICE In-Circuit Emulator System

    229
  • 20.8 MPLAB ICD 3 In-Circuit Debugger System

    229
  • 20.9 PICkit 3 In-Circuit Debugger/ Programmer

    229
  • 20.10 MPLAB PM3 Device Programmer

    229
  • 20.11 Demonstration/Development Boards, Evaluation Kits and Starter Kits

    230
  • 20.12 Third-Party Development Tools

    230
• 21.0 Electrical Characteristics

  231
  • Absolute Maximum Ratings(†)

    231
  • 21.1 DC Characteristics

    231
    • TABLE 21-1: Operating MIPS vs. Voltage

      231
    • TABLE 21-2: Thermal Operating Conditions

      232
    • TABLE 21-3: Thermal Packaging Characteristics

      232
    • TABLE 21-4: DC Temperature and Voltage specifications

      232
    • TABLE 21-5: DC Characteristics: Operating Current (Idd)

      233
    • TABLE 21-6: DC Characteristics: Idle Current (iidle)

      235
    • TABLE 21-7: DC Characteristics: Power-Down Current (Ipd)

      237
    • TABLE 21-8: DC Characteristics: I/O Pin Input Specifications

      238
    • TABLE 21-9: DC Characteristics: I/O Pin Output Specifications

      239
    • TABLE 21-10: DC Characteristics: Program and EEPROM

      239
  • 21.2 AC Characteristics and Timing Parameters

    240
    • TABLE 21-11: Temperature and Voltage Specifications – AC

      240
    • FIGURE 21-1: Load Conditions for Device Timing Specifications

      240
    • FIGURE 21-2: External Clock Timing

      240
    • TABLE 21-12: External Clock Timing Requirements

      241
    • TABLE 21-13: PLL Clock Timing Specifications (Vdd = 3.0 AND 5.0V )

      242
    • TABLE 21-14: Internal Clock Timing examples

      242
    • TABLE 21-15: AC Characteristics: Internal RC Accuracy

      243
    • TABLE 21-16: AC Characteristics: Internal RC Jitter

      244
    • FIGURE 21-3: CLKO and I/O Timing Characteristics

      245
    • TABLE 21-17: CLKO and I/O Timing Requirements

      245
    • FIGURE 21-4: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing Characteristics

      246
    • TABLE 21-18: Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and Timing Requirements

      247
    • FIGURE 21-5: band gap Start-up Time Characteristics

      248
    • TABLE 21-19: band gap Start-up Time Requirements

      248
    • FIGURE 21-6: Timerx External Clock Timing Characteristics

      249
    • TABLE 21-20: Timer1 External Clock Timing Requirements

      249
    • TABLE 21-21: Timer2 External Clock Timing Requirements

      250
    • TABLE 21-22: Timer3 External Clock Timing Requirements

      250
    • FIGURE 21-7: INPUT CAPTURE x (ICx) TIMING Characteristics

      251
    • TABLE 21-23: Input Capture x timing requirements

      251
    • FIGURE 21-8: Output Compare x (OCx) Module Timing Characteristics

      251
    • TABLE 21-24: Output Compare x Module timing requirements

      251
    • FIGURE 21-9: OCx/PWM Module Timing Characteristics

      252
    • TABLE 21-25: Simple OCx/PWM MODE Timing Requirements

      252
    • FIGURE 21-10: Power Supply PWM Module fault Timing Characteristics

      253
    • FIGURE 21-11: Power Supply PWM Module Timing Characteristics

      253
    • TABLE 21-26: Power Supply PWM Module Timing Requirements

      253
    • FIGURE 21-12: SPIx Module Master Mode (CKE = 0) Timing Characteristics

      254
    • TABLE 21-27: SPIx Master mode (cke = 0) Timing requirements

      254
    • FIGURE 21-13: SPIx Module Master Mode (CKE = 1) Timing Characteristics

      255
    • TABLE 21-28: SPIx Module Master mode (cke = 1) Timing requirements

      255
    • FIGURE 21-14: SPIx Module Slave Mode (CKE = 0) Timing Characteristics

      256
    • TABLE 21-29: SPIx Module Slave mode (cke = 0) Timing requirements

      256
    • FIGURE 21-15: SPIx Module Slave Mode (CKE = 1) Timing Characteristics

      257
    • TABLE 21-30: SPIx Module Slave mode (cke = 1) Timing requirements

      258
    • FIGURE 21-16: I2C™ Bus Start/Stop Bits Timing Characteristics (Master mode)

      259
    • FIGURE 21-17: I2C™ Bus Data Timing Characteristics (Master mode)

      259
    • TABLE 21-31: I2C™ Bus Data Timing Requirements (Master Mode)

      260
    • FIGURE 21-18: I2C™ Bus Start/Stop Bits Timing Characteristics (slave mode)

      261
    • FIGURE 21-19: I2C™ Bus Data Timing Characteristics (slave mode)

      261
    • TABLE 21-32: I2C™ Bus Data Timing Requirements (Slave Mode)

      262
    • TABLE 21-33: 10-bit High-speed a/d Module Specifications

      263
    • FIGURE 21-20: A/d Conversion Timing Per Input

      264
    • TABLE 21-34: Comparator Operating Conditions

      265
    • TABLE 21-35: comparator AC AND DC Specifications

      265
    • TABLE 21-36: DAC DC Specifications

      265
    • TABLE 21-37: DAC AC Specifications

      265
• 22.0 Package Marking Information

  267
  • 28-Lead Plastic Quad Flat, No Lead Package (MM) - 6x6x0.9 mm Body (QFN-S) With 0.40 mm Contact Length

    268
  • 28-Lead Skinny Plastic Dual In-line (SP) – 300 mil Body (PDIP)

    269
  • 28-Lead Plastic Small Outline (SO) – Wide, 300 mil Body (SOIC)

    270
  • 44-Lead Plastic Thin Quad Flatpack (PT) 10x10x1 mm Body, 1.0/0.10 mm Lead Form (TQFP)

    271
  • 44-Lead Plastic Quad Flat, No Lead Package (ML) - 8x8 mm Body (QFN)

    272
• The Microchip Web Site

  273
• Customer Change Notification Service

  273
• Customer Support

  273
• Appendix A: Revision History

  275
  • Revision A (June 2006)

    275
  • Revision B (August 2006)

    275
  • Revision C (November 2006)

    275
  • Revision D (March 2014)

    275
• INDEX

  277
• Product Identification System

  283
• Worldwide Sales and Service

  286