Manuali utente per Microchip Technology DM160214

Sommario

• High-Performance RISC CPU:

  3
• Special Microcontroller Features:

  3
• PIC16LF1946/47 Low-Power Features:

  3
• Peripheral Features:

  3
• Peripheral Features (Continued):

  4
• Pin Diagram – 64-Pin TQFP/QFN (PIC16(L)F1946/47)

  5
• Table of Contents

  8
• Most Current Data Sheet

  9
• Errata

  9
• Customer Notification System

  9
• 1.0 Device Overview

  11
  • TABLE 1-1: Device Peripheral Summary

    11
  • FIGURE 1-1: PIC16(L)F1946/47 Block Diagram

    12
  • TABLE 1-2: PIC16(L)F1946/47 Pinout Description

    13
• 2.0 Enhanced Mid-Range CPU

  19
  • 2.1 Automatic Interrupt Context Saving

    19
  • 2.2 16-level Stack with Overflow and Underflow

    19
  • 2.3 File Select Registers

    19
  • 2.4 Instruction Set

    19
    • FIGURE 2-1: Core Block Diagram

      20
• 3.0 Memory Organization

  21
  • 3.1 Program Memory Organization

    21
    • TABLE 3-1: Device Sizes and Addresses

      21
    • FIGURE 3-1: Program Memory Map And Stack For PIC16(L)F1946

      22
    • FIGURE 3-2: Program Memory Map And Stack For PIC16(L)F1947

      22
    • 3.1.1 Reading Program Memory as Data

      23
      • EXAMPLE 3-1: RETLW Instruction

        23
      • EXAMPLE 3-2: Accessing Program Memory Via FSR

        24
  • 3.2 Data Memory Organization

    24
    • 3.2.1 Core Registers

      24
      • TABLE 3-2: Core Registers

        24
  • 3.3 Register Definitions: Status

    25
    • Register 3-1: STATUS: STATUS Register

      25
    • 3.3.1 Special Function Register

      26
    • 3.3.2 General Purpose RAM

      26
    • 3.3.3 Common RAM

      26
      • FIGURE 3-3: Banked Memory Partitioning

        26
    • 3.3.4 Device Memory Maps

      26
      • TABLE 3-3: Memory Map Tables

        26
      • TABLE 3-4: PIC16(L)F1946/47 Memory Map, Banks 0-7

        27
      • TABLE 3-5: PIC16(L)F1946/47 Memory Map, Banks 8-15

        28
      • TABLE 3-6: PIC16(L)F1946/47 Memory Map, Banks 16-23

        29
      • TABLE 3-7: PIC16(L)F1946/47 Memory Map, Banks 24-31

        30
      • TABLE 3-8: PIC16(L)F1946/47 Memory Map, Bank 15

        31
      • TABLE 3-9: PIC16(L)F1946/47 Memory Map, Bank 31

        31
    • 3.3.5 Special Function Registers Summary

      32
      • TABLE 3-10: Special Function Register Summary

        33
  • 3.4 PCL and PCLATH

    48
    • FIGURE 3-4: Loading Of PC In Different Situations

      48
    • 3.4.1 Modifying PCL

      48
    • 3.4.2 computed goto

      48
    • 3.4.3 Computed Function Calls

      48
    • 3.4.4 Branching

      48
  • 3.5 Stack

    49
    • 3.5.1 Accessing the Stack

      49
      • FIGURE 3-5: Accessing the Stack Example 1

        49
      • FIGURE 3-6: Accessing the Stack Example 2

        50
      • FIGURE 3-7: Accessing the Stack Example 3

        50
      • FIGURE 3-8: Accessing the Stack Example 4

        51
    • 3.5.2 Overflow/Underflow Reset

      51
  • 3.6 Indirect Addressing

    51
    • FIGURE 3-9: Indirect Addressing

      52
    • 3.6.1 Traditional Data Memory

      53
      • FIGURE 3-10: Traditional Data Memory Map

        53
    • 3.6.2 Linear Data Memory

      54
      • FIGURE 3-11: Linear Data Memory Map

        54
    • 3.6.3 Program Flash Memory

      54
      • FIGURE 3-12: Program Flash Memory Map

        54
• 4.0 Device Configuration

  55
  • 4.1 Configuration Words

    55
  • 4.2 Register Definitions: Configuration Words

    56
    • Register 4-1: CONFIG1: Configuration Word 1

      56
    • Register 4-2: CONFIG2: Configuration Word 2

      58
  • 4.3 Code Protection

    59
    • 4.3.1 Program Memory Protection

      59
    • 4.3.2 Data EEPROM Protection

      59
  • 4.4 Write Protection

    59
  • 4.5 User ID

    59
  • 4.6 Device ID and Revision ID

    60
  • 4.7 Register Definitions: Device ID

    60
    • Register 4-3: DEVICEID: Device ID Register

      60
• 5.0 Oscillator Module (With Fail-Safe Clock Monitor)

  61
  • 5.1 Overview

    61
    • FIGURE 5-1: Simplified PIC® MCU Clock Source Block Diagram

      62
  • 5.2 Clock Source Types

    63
    • 5.2.1 External Clock Sources

      63
      • FIGURE 5-2: External Clock (EC) Mode Operation

        63
      • FIGURE 5-3: Quartz Crystal Operation (LP, XT or HS Mode)

        64
      • FIGURE 5-4: Ceramic Resonator Operation (XT or HS Mode)

        64
      • FIGURE 5-5: Quartz Crystal Operation (Timer1 Oscillator)

        65
      • FIGURE 5-6: External RC Modes

        65
    • 5.2.2 Internal Clock Sources

      66
      • FIGURE 5-7: Internal Oscillator Switch Timing

        69
  • 5.3 Clock Switching

    70
    • 5.3.1 System Clock Select (SCS) Bits

      70
    • 5.3.2 Oscillator Start-up Time-out Status (OSTS) Bit

      70
    • 5.3.3 Timer1 Oscillator

      70
    • 5.3.4 Timer1 Oscillator Ready (T1OSCR) Bit

      70
  • 5.4 Two-Speed Clock Start-up Mode

    71
    • 5.4.1 Two-Speed Start-up Mode Configuration

      71
      • TABLE 5-1: Oscillator Switching Delays

        71
    • 5.4.2 Two-speed Start-up Sequence

      72
    • 5.4.3 Checking Two-Speed Clock Status

      72
      • FIGURE 5-8: Two-Speed Start-up

        72
  • 5.5 Fail-Safe Clock Monitor

    73
    • FIGURE 5-9: FSCM Block Diagram

      73
    • 5.5.1 Fail-Safe Detection

      73
    • 5.5.2 Fail-Safe Operation

      73
    • 5.5.3 Fail-Safe Condition Clearing

      73
    • 5.5.4 Reset or Wake-up from Sleep

      73
      • FIGURE 5-10: FSCM Timing Diagram

        74
  • 5.6 Register Definitions: Oscillator Control

    75
    • Register 5-1: OSCCON: Oscillator Control Register

      75
    • Register 5-2: OSCSTAT: Oscillator Status Register

      76
    • Register 5-3: OSCTUNE: Oscillator Tuning Register

      77
    • TABLE 5-2: Summary of Registers Associated with Clock Sources

      77
    • TABLE 5-3: Summary of Configuration Word with Clock Sources

      77
• 6.0 Resets

  79
  • FIGURE 6-1: Simplified Block Diagram Of On-Chip Reset Circuit

    79
  • 6.1 Power-on Reset (POR)

    80
    • 6.1.1 Power-up Timer (PWRT)

      80
  • 6.2 Brown-Out Reset (BOR)

    80
    • TABLE 6-1: BOR Operating Modes

      80
    • 6.2.1 BOR is Always On

      80
    • 6.2.2 BOR is Off in Sleep

      80
    • 6.2.3 BOR Controlled by Software

      80
      • FIGURE 6-2: Brown-Out Situations

        81
  • 6.3 Register Definitions: BOR Control

    81
    • Register 6-1: BORCON: Brown-out Reset Control Register

      81
  • 6.4 MCLR

    82
    • TABLE 6-2: MCLR Configuration

      82
    • 6.4.1 MCLR Enabled

      82
    • 6.4.2 MCLR Disabled

      82
  • 6.5 Watchdog Timer (WDT) Reset

    82
  • 6.6 RESET Instruction

    82
  • 6.7 Stack Overflow/Underflow Reset

    82
  • 6.8 Programming Mode Exit

    82
  • 6.9 Power-Up Timer

    82
  • 6.10 Start-up Sequence

    82
    • FIGURE 6-3: Reset Start-Up Sequence

      83
  • 6.11 Determining the Cause of a Reset

    84
    • TABLE 6-3: Reset Status Bits and Their Significance

      84
    • TABLE 6-4: Reset Condition for Special Registers(2)

      84
  • 6.12 Power Control (PCON) Register

    85
  • 6.13 Register Definitions: Power Control

    85
    • Register 6-2: PCON: Power Control Register

      85
    • TABLE 6-5: Summary Of Registers Associated With Resets

      86
• 7.0 Interrupts

  87
  • FIGURE 7-1: Interrupt Logic

    87
  • 7.1 Operation

    88
  • 7.2 Interrupt Latency

    88
    • FIGURE 7-2: Interrupt Latency

      89
    • FIGURE 7-3: INT Pin Interrupt Timing

      90
  • 7.3 Interrupts During Sleep

    91
  • 7.4 INT Pin

    91
  • 7.5 Automatic Context Saving

    91
  • 7.6 Register Definitions: Interrupt Control

    92
    • Register 7-1: INTCON: Interrupt Control Register

      92
    • Register 7-2: PIE1: Peripheral Interrupt Enable Register 1

      93
    • Register 7-3: PIE2: Peripheral Interrupt Enable Register 2

      94
    • Register 7-4: PIE3: Peripheral Interrupt Enable Register 3

      95
    • Register 7-5: PIE4: Peripheral Interrupt Enable Register 4

      96
    • Register 7-6: PIR1: Peripheral Interrupt Request Register 1

      97
    • Register 7-7: PIR2: Peripheral Interrupt Request Register 2

      98
    • Register 7-8: PIR3: Peripheral Interrupt Request Register 3

      99
    • Register 7-9: PIR4: Peripheral Interrupt Request Register 4

      100
    • TABLE 7-1: Summary of Registers Associated with Interrupts

      101
• 8.0 Low Dropout (LDO) Voltage Regulator

  103
  • TABLE 8-1: VCAPEN Select Bit

    103
  • TABLE 8-2: Summary of Configuration Word with LDO

    103
• 9.0 Power-Down Mode (Sleep)

  105
  • 9.1 Wake-up from Sleep

    105
    • 9.1.1 Wake-up Using Interrupts

      106
      • FIGURE 9-1: Wake-Up From Sleep Through Interrupt

        106
      • TABLE 9-1: Summary of Registers Associated with Power-Down Mode

        106
• 10.0 Watchdog Timer (WDT)

  107
  • FIGURE 10-1: Watchdog Timer Block Diagram

    107
  • 10.1 Independent Clock Source

    108
  • 10.2 WDT Operating Modes

    108
    • 10.2.1 WDT Is Always On

      108
    • 10.2.2 WDT Is Off In Sleep

      108
    • 10.2.3 WDT Controlled By Software

      108
      • TABLE 10-1: WDT Operating Modes

        108
  • 10.3 Time-Out Period

    108
  • 10.4 Clearing the WDT

    108
  • 10.5 Operation During Sleep

    108
    • TABLE 10-2: WDT Clearing Conditions

      108
  • 10.6 Register Definitions: Watchdog Control

    109
    • Register 10-1: WDTCON: Watchdog Timer Control Register

      109
    • TABLE 10-3: Summary of Registers Associated with Watchdog Timer

      110
    • TABLE 10-4: Summary of Configuration Word with Watchdog Timer

      110
• 11.0 Data EEPROM and Flash Program Memory Control

  111
  • 11.1 EEADRL and EEADRH Registers

    111
    • 11.1.1 EECON1 and EECON2 Registers

      111
  • 11.2 Using the Data EEPROM

    112
    • 11.2.1 Reading the Data EEPROM Memory

      112
      • EXAMPLE 11-1: Data EEPROM Read

        112
    • 11.2.2 Writing to the Data EEPROM Memory

      112
    • 11.2.3 Protection Against Spurious Write

      112
    • 11.2.4 Data EEPROM Operation During Code-Protect

      112
      • EXAMPLE 11-2: Data EEPROM Write

        113
      • FIGURE 11-1: Flash Program Memory Read Cycle Execution

        113
  • 11.3 Flash Program Memory Overview

    114
    • 11.3.1 Reading the Flash Program Memory

      114
      • TABLE 11-1: Flash Memory Organization By Device

        114
      • EXAMPLE 11-3: Flash Program Memory Read

        115
    • 11.3.2 Erasing Flash Program Memory

      116
    • 11.3.3 Writing to Flash Program Memory

      116
      • FIGURE 11-2: Block Writes to Flash Program Memory With 32 write latches

        117
      • EXAMPLE 11-4: Erasing One Row of Program Memory -

        118
      • EXAMPLE 11-5: Writing to Flash Program Memory

        119
  • 11.4 Modifying Flash Program Memory

    120
  • 11.5 User ID, Device ID and Configuration Word Access

    120
    • TABLE 11-2: User ID, Device ID and Configuration Word Access (CFGS = 1)

      120
  • 11.6 Write Verify

    121
    • EXAMPLE 11-6: EEPROM Write Verify

      121
  • 11.7 Register Definitions: Data EEPROM Control

    122
    • Register 11-1: EEDATL: EEPROM Data Low Byte Register

      122
    • Register 11-2: EEDATH: EEPROM Data High Byte Register

      122
    • Register 11-3: EEADRL: EEPROM Address Low Byte Register

      123
    • Register 11-4: EEADRH: EEPROM Address High Byte Register

      123
    • Register 11-5: EECON1: EEPROM Control 1 Register

      124
    • Register 11-6: EECON2: EEPROM Control 2 Register

      125
    • TABLE 11-3: Summary of Registers Associated with Data EEPROM

      125
• 12.0 I/O Ports

  127
  • TABLE 12-1: Port Availability Per Device

    127
  • FIGURE 12-1: Generic I/O Port Operation

    127
  • EXAMPLE 12-1: Initializing PORTA

    127
  • 12.1 Alternate Pin Function

    128
  • 12.2 Register Definitions: Alternate Pin Function Control

    129
    • Register 12-1: APFCON: Alternate Pin Function Control Register

      129
  • 12.3 PORTA Registers

    130
    • 12.3.1 ANSELA Register

      130
    • 12.3.2 PORTA Functions and Output Priorities

      130
      • TABLE 12-2: PORTA Output Priority

        130
  • 12.4 Register Definitions: PORTA

    131
    • Register 12-2: PORTA: PORTA Register

      131
    • Register 12-3: TRISA: PORTA Tri-State Register

      131
    • Register 12-4: LATA: PORTA Data Latch Register

      131
    • Register 12-5: ANSELA: PORTA Analog Select Register

      132
    • TABLE 12-3: Summary of Registers Associated with PORTA

      132
    • TABLE 12-4: Summary of Configuration Word with PORTA

      132
  • 12.5 PORTB Registers

    133
    • 12.5.1 Weak Pull-Ups

      133
    • 12.5.2 Interrupt-on-Change

      133
    • 12.5.3 PORTB Functions and Output Priorities

      133
      • TABLE 12-5: PORTB Output Priority

        133
  • 12.6 Register Definitions: PORTB

    134
    • Register 12-6: PORTB: PORTB Register

      134
    • Register 12-7: TRISB: PORTB Tri-State Register

      134
    • Register 12-8: LATB: PORTB Data Latch Register

      134
    • Register 12-9: WPUB: Weak Pull-up PORTB Register

      135
    • TABLE 12-6: Summary of Registers Associated with PORTB

      135
  • 12.7 PORTC Registers

    136
    • 12.7.1 PORTC Functions and Output Priorities

      136
      • TABLE 12-7: PORTC Output Priority

        136
  • 12.8 Register Definitions: PORTC

    137
    • Register 12-10: PORTC: PORTC Register

      137
    • Register 12-11: TRISC: PORTC Tri-State Register

      137
    • Register 12-12: LATC: PORTC Data Latch Register

      137
    • TABLE 12-8: Summary of Registers Associated with PORTC

      138
  • 12.9 PORTD Registers

    139
    • 12.9.1 PORTD Functions and Output Priorities

      139
      • TABLE 12-9: PORTD Output Priority

        139
  • 12.10 Register Definitions: PORTD

    140
    • Register 12-13: PORTD: PORTD Register

      140
    • Register 12-14: TRISD: PORTD Tri-State Register

      140
    • Register 12-15: LATD: PORTD Data Latch Register

      140
    • TABLE 12-10: Summary of Registers Associated with PORTD

      141
  • 12.11 PORTE Registers

    142
    • 12.11.1 ANSELE Register

      142
    • 12.11.2 PORTE Functions and Output Priorities

      142
      • TABLE 12-11: PORTE Output Priority

        142
  • 12.12 Register Definitions: PORTE

    143
    • Register 12-16: PORTE: PORTE Register

      143
    • Register 12-17: TRISE: PORTE Tri-State Register

      143
    • Register 12-18: LATE: PORTE Data Latch Register

      144
    • Register 12-19: ANSELE: PORTE Analog Select Register

      144
    • TABLE 12-12: Summary of Registers Associated with PORTE

      144
  • 12.13 PORTF Registers

    145
    • 12.13.1 ANSELF Register

      145
    • 12.13.2 PORTF Functions and Output Priorities

      145
      • TABLE 12-13: PORTF Output Priority

        145
  • 12.14 Register Definitions: PORTF

    146
    • Register 12-20: PORTF: PORTF Register

      146
    • Register 12-21: TRISF: PORTF Tri-State Register

      146
    • Register 12-22: LATF: PORTF Data Latch Register

      146
    • Register 12-23: ANSELF: PORTF Analog Select Register

      147
    • TABLE 12-14: Summary of Registers Associated with PORTF

      147
    • TABLE 12-15: Summary of Configuration Word Associated with PORTF

      147
  • 12.15 PORTG Registers

    148
    • 12.15.1 ANSELG Register

      148
    • 12.15.2 PORTG Functions and Output Priorities

      148
      • TABLE 12-16: PORTG Output Priority

        148
  • 12.16 Register Definitions: PORTG

    149
    • Register 12-24: PORTG: PORTG Register

      149
    • Register 12-25: TRISG: PORTG Tri-State Register

      149
    • Register 12-26: LATG: PORTG Data Latch Register

      149
    • Register 12-27: ANSELG: PORTG Analog Select Register

      150
    • Register 12-28: WPUG: Weak Pull-up PORTG Register

      150
    • TABLE 12-17: Summary of Registers Associated with PORTG

      151
• 13.0 Interrupt-On-Change

  153
  • 13.1 Enabling the Module

    153
  • 13.2 Individual Pin Configuration

    153
  • 13.3 Interrupt Flags

    153
  • 13.4 Clearing Interrupt Flags

    153
    • EXAMPLE 13-1: Clearing Interrupt Flags (PORTA Example)

      153
  • 13.5 Operation in Sleep

    153
    • FIGURE 13-1: Interrupt-On-Change Block Diagram

      154
  • 13.6 Register Definitions: Interrupt-on-Change Control

    155
    • Register 13-1: IOCBP: Interrupt-on-Change PORTB Positive Edge Register

      155
    • Register 13-2: IOCBN: Interrupt-on-Change PORTB Negative Edge Register

      155
    • Register 13-3: IOCBF: Interrupt-on-Change PORTB Flag Register

      155
    • TABLE 13-1: Summary of Registers Associated with Interrupt-on-Change

      156
• 14.0 Fixed Voltage Reference (FVR)

  157
  • 14.1 Independent Gain Amplifiers

    157
  • 14.2 FVR Stabilization Period

    157
    • FIGURE 14-1: Voltage Reference Block Diagram

      157
  • 14.3 Register Definitions: FVR Control

    158
    • Register 14-1: FVRCON: Fixed Voltage Reference Control Register

      158
    • TABLE 14-1: Summary of Registers Associated with the Fixed Voltage Reference

      158
• 15.0 Temperature Indicator Module

  159
  • 15.1 Circuit Operation

    159
    • EQUATION 15-1: Vout Ranges

      159
    • FIGURE 15-1: Temperature Circuit Diagram

      159
  • 15.2 Minimum Operating Vdd

    159
    • TABLE 15-1: Recommended Vdd vs. Range

      159
  • 15.3 Temperature Output

    159
  • 15.4 ADC Acquisition Time

    160
    • TABLE 15-2: Summary of Registers Associated with the Temperature Indicator

      160
• 16.0 Analog-to-Digital Converter (ADC) Module

  161
  • FIGURE 16-1: ADC Block Diagram

    162
  • 16.1 ADC Configuration

    163
    • 16.1.1 Port Configuration

      163
    • 16.1.2 Channel Selection

      163
    • 16.1.3 ADC Voltage Reference

      163
    • 16.1.4 Conversion Clock

      163
      • TABLE 16-1: ADC Clock Period (Tad) Vs. Device Operating Frequencies

        164
      • FIGURE 16-2: Analog-to-Digital Conversion Tad Cycles

        164
    • 16.1.5 Interrupts

      165
    • 16.1.6 Result Formatting

      165
      • FIGURE 16-3: 10-Bit A/D Conversion Result Format

        165
  • 16.2 ADC Operation

    166
    • 16.2.1 Starting a Conversion

      166
    • 16.2.2 Completion of a Conversion

      166
    • 16.2.3 Terminating a conversion

      166
  • 16.3 ADC Operation During Sleep

    166
    • 16.3.1 Special Event Trigger

      166
      • TABLE 16-2: Special Event Trigger

        166
    • 16.3.2 A/D Conversion Procedure

      167
      • EXAMPLE 16-1: A/D Conversion

        167
  • 16.4 Register Definitions: ADC Control

    168
    • Register 16-1: ADCON0: A/D Control Register 0

      168
    • Register 16-2: ADCON1: A/D Control Register 1

      169
    • Register 16-3: ADRESH: ADC Result Register High (ADRESH) ADFM = 0

      170
    • Register 16-4: ADRESL: ADC Result Register Low (ADRESL) ADFM = 0

      170
    • Register 16-5: ADRESH: ADC Result Register High (ADRESH) ADFM = 1

      171
    • Register 16-6: ADRESL: ADC Result Register Low (ADRESL) ADFM = 1

      171
  • 16.5 A/D Acquisition Requirements

    172
    • EQUATION 16-1: Acquisition Time Example

      172
    • FIGURE 16-4: Analog Input Model

      173
    • FIGURE 16-5: ADC Transfer Function

      173
    • TABLE 16-3: Summary of Registers Associated with ADC

      174
• 17.0 Digital-to-Analog Converter (DAC) Module

  175
  • 17.1 Output Voltage Selection

    175
    • EQUATION 17-1: DAC Output Voltage

      175
  • 17.2 Ratiometric Output Level

    175
  • 17.3 DAC Voltage Reference Output

    175
    • FIGURE 17-1: Digital-to-Analog Converter Block Diagram

      176
    • FIGURE 17-2: Voltage Reference Output Buffer Example

      176
  • 17.4 Low-Power Voltage State

    177
    • 17.4.1 Output Clamped to Positive Voltage Source

      177
    • 17.4.2 Output Clamped to Negative Voltage Source

      177
      • FIGURE 17-3: Output Voltage Clamping Examples

        177
  • 17.5 Operation During Sleep

    177
  • 17.6 Effects of a Reset

    177
  • 17.7 Register Definitions: DAC Control

    178
    • Register 17-1: DACCON0: Voltage Reference Control Register 0

      178
    • Register 17-2: DACCON1: Voltage Reference Control Register 1

      178
    • TABLE 17-1: Summary of Registers Associated with the DAC Module

      178
• 18.0 Comparator Module

  179
  • 18.1 Comparator Overview

    179
    • TABLE 18-1: Comparator Availability Per Device

      179
    • FIGURE 18-1: Single Comparator

      179
    • FIGURE 18-2: Comparator Module Simplified Block Diagram

      180
  • 18.2 Comparator Control

    181
    • 18.2.1 Comparator Enable

      181
    • 18.2.2 Comparator Output Selection

      181
    • 18.2.3 Comparator Output Polarity

      181
      • TABLE 18-2: Comparator Output State vs. Input Conditions

        181
    • 18.2.4 Comparator Speed/Power Selection

      181
  • 18.3 Comparator Hysteresis

    182
  • 18.4 Timer1 Gate Operation

    182
    • 18.4.1 Comparator Output Synchronization

      182
  • 18.5 Comparator Interrupt

    182
  • 18.6 Comparator Positive Input Selection

    182
  • 18.7 Comparator Negative Input Selection

    183
  • 18.8 Comparator Response Time

    183
  • 18.9 Interaction with ECCP Logic

    183
  • 18.10 Analog Input Connection Considerations

    183
    • FIGURE 18-3: Analog Input Model

      184
  • 18.11 Register Definitions: Comparator Control

    185
    • Register 18-1: CMxCON0: Comparator Cx Control Register 0

      185
    • Register 18-2: CMxCON1: Comparator Cx Control Register 1

      186
    • Register 18-3: CMOUT: Comparator Output Register

      186
    • TABLE 18-3: Summary of Registers Associated with Comparator Module

      187
• 19.0 SR Latch

  189
  • 19.1 Latch Operation

    189
  • 19.2 Latch Output

    189
  • 19.3 Effects of a Reset

    189
    • FIGURE 19-1: SR Latch Simplified Block Diagram

      190
    • TABLE 19-1: SRCLK Frequency table

      191
  • 19.4 Register Definitions: SR Latch Control

    192
    • Register 19-1: SRCON0: SR Latch Control 0 Register

      192
    • Register 19-2: SRCON1: SR Latch Control 1 Register

      193
    • TABLE 19-2: Summary of Registers Associated with SR Latch Module

      193
• 20.0 Timer0 Module

  195
  • 20.1 Timer0 Operation

    195
    • 20.1.1 8-bit Timer mode

      195
    • 20.1.2 8-Bit Counter Mode

      195
      • FIGURE 20-1: Block Diagram of the Timer0

        195
    • 20.1.3 Software Programmable Prescaler

      196
    • 20.1.4 Timer0 Interrupt

      196
    • 20.1.5 8-Bit Counter Mode Synchronization

      196
    • 20.1.6 Operation During Sleep

      196
  • 20.2 Register Definitions: Option Register

    197
    • Register 20-1: OPTION_REG: OPTION Register

      197
    • TABLE 20-1: Summary of Registers Associated with Timer0

      197
• 21.0 Timer1 Module with Gate Control

  199
  • FIGURE 21-1: Timer1 Block Diagram

    199
  • 21.1 Timer1 Operation

    200
    • TABLE 21-1: Timer1 Enable Selections

      200
  • 21.2 Clock Source Selection

    200
    • 21.2.1 Internal Clock Source

      200
    • 21.2.2 External Clock Source

      200
      • TABLE 21-2: Clock Source Selections

        200
  • 21.3 Timer1 Prescaler

    201
  • 21.4 Timer1 Oscillator

    201
  • 21.5 Timer1 Operation in Asynchronous Counter Mode

    201
    • 21.5.1 Reading and Writing Timer1 in Asynchronous Counter Mode

      201
  • 21.6 Timer1 Gate

    201
    • 21.6.1 Timer1 Gate Enable

      201
      • TABLE 21-3: Timer1 Gate Enable Selections

        201
    • 21.6.2 Timer1 Gate Source Selection

      202
      • TABLE 21-4: Timer1 Gate Sources

        202
    • 21.6.3 Timer1 Gate Toggle Mode

      202
    • 21.6.4 Timer1 Gate Single-Pulse Mode

      202
    • 21.6.5 Timer1 Gate Value Status

      202
    • 21.6.6 Timer1 Gate Event Interrupt

      202
  • 21.7 Timer1 Interrupt

    203
  • 21.8 Timer1 Operation During Sleep

    203
  • 21.9 ECCP/CCP Capture/Compare Time Base

    203
  • 21.10 ECCP/CCP Special Event Trigger

    203
    • FIGURE 21-2: Timer1 Incrementing Edge

      203
    • FIGURE 21-3: Timer1 Gate Enable Mode

      204
    • FIGURE 21-4: Timer1 Gate Toggle Mode

      204
    • FIGURE 21-5: Timer1 Gate Single-Pulse Mode

      205
    • FIGURE 21-6: Timer1 Gate Single-Pulse and Toggle Combined Mode

      206
  • 21.11 Register Definitions: Timer1 Control

    207
    • Register 21-1: T1CON: Timer1 Control Register

      207
    • Register 21-2: T1GCON: Timer1 Gate Control Register

      208
    • TABLE 21-5: Summary of Registers Associated with Timer1

      209
• 22.0 Timer2/4/6 Modules

  211
  • FIGURE 22-1: Timer2/4/6 Block Diagram

    211
  • 22.1 Timer2/4/6 Operation

    212
  • 22.2 Timer2/4/6 Interrupt

    212
  • 22.3 Timer2/4/6 Output

    212
  • 22.4 Timer2/4/6 Operation During Sleep

    212
  • 22.5 Register Definitions: Timer2 Control

    213
    • Register 22-1: TxCON: Timer2/Timer4/Timer6 Control Register

      213
    • TABLE 22-1: Summary of Registers Associated With Timer2/4/6

      214
• 23.0 Capture/Compare/PWM Modules

  215
  • TABLE 23-1: PWM Resources

    215
  • 23.1 Capture Mode

    216
    • 23.1.1 CCP pin Configuration

      216
      • FIGURE 23-1: Capture Mode Operation Block Diagram

        216
    • 23.1.2 Timer1 Mode Resource

      216
    • 23.1.3 Software Interrupt Mode

      216
    • 23.1.4 CCP Prescaler

      216
      • EXAMPLE 23-1: Changing Between Capture Prescalers

        216
    • 23.1.5 Capture During Sleep

      217
    • 23.1.6 Alternate Pin Locations

      217
      • TABLE 23-2: Summary of Registers Associated with Capture

        217
  • 23.2 Compare Mode

    218
    • FIGURE 23-2: Compare Mode Operation Block Diagram

      218
    • 23.2.1 CCP Pin Configuration

      218
    • 23.2.2 Timer1 Mode Resource

      218
    • 23.2.3 Software Interrupt Mode

      218
    • 23.2.4 Special Event Trigger

      218
      • TABLE 23-3: Special Event Trigger

        218
    • 23.2.5 Compare During Sleep

      219
    • 23.2.6 Alternate Pin Locations

      219
      • TABLE 23-4: Summary of Registers Associated with Compare

        219
  • 23.3 PWM Overview

    220
    • 23.3.1 Standard PWM Operation

      220
      • FIGURE 23-3: CCP PWM Output Signal

        220
      • FIGURE 23-4: Simplified PWM Block Diagram

        220
    • 23.3.2 Setup for PWM Operation

      221
    • 23.3.3 Timer2/4/6 Timer Resource

      221
    • 23.3.4 PWM Period

      221
      • EQUATION 23-1: PWM Period

        221
    • 23.3.5 PWM Duty Cycle

      221
      • EQUATION 23-2: Pulse Width

        221
      • EQUATION 23-3: Duty Cycle Ratio

        221
    • 23.3.6 PWM Resolution

      222
      • EQUATION 23-4: PWM Resolution

        222
      • TABLE 23-5: Example PWM Frequencies and Resolutions (Fosc = 32 MHz)

        222
      • TABLE 23-6: Example PWM Frequencies and Resolutions (Fosc = 20 MHz)

        222
      • TABLE 23-7: Example PWM Frequencies and Resolutions (Fosc = 8 MHz)

        222
    • 23.3.7 Operation in Sleep Mode

      223
    • 23.3.8 Changes in System Clock Frequency

      223
    • 23.3.9 Effects of Reset

      223
    • 23.3.10 Alternate Pin Locations

      223
      • TABLE 23-8: Summary of Registers Associated with Standard PWM

        223
  • 23.4 PWM (Enhanced Mode)

    224
    • FIGURE 23-5: Example Simplified Block Diagram of the Enhanced PWM Mode

      224
    • TABLE 23-9: Example Pin Assignments for Various PWM Enhanced Modes

      225
    • FIGURE 23-6: Example PWM (Enhanced Mode) Output Relationships (Active-High State)

      225
    • FIGURE 23-7: Example Enhanced PWM Output Relationships (Active-Low State)

      226
    • 23.4.1 Half-Bridge Mode

      227
      • FIGURE 23-8: Example of Half-Bridge PWM Output

        227
      • FIGURE 23-9: Example of Half-Bridge Applications

        227
    • 23.4.2 Full-Bridge Mode

      228
      • FIGURE 23-10: Example of Full-Bridge Application

        228
      • FIGURE 23-11: Example of Full-Bridge PWM Output

        229
      • FIGURE 23-12: Example of PWM Direction Change

        230
      • FIGURE 23-13: Example of PWM Direction Change at Near 100% Duty Cycle

        231
    • 23.4.3 Enhanced PWM Auto-shutdown mode

      232
      • FIGURE 23-14: PWM Auto-shutdown With Firmware Restart (PxRSEN = 0)

        233
    • 23.4.4 Auto-Restart Mode

      233
      • FIGURE 23-15: PWM Auto-shutdown With Auto-Restart (PxRSEN = 1)

        233
    • 23.4.5 Programmable Dead-Band Delay Mode

      234
      • FIGURE 23-16: Example of Half-Bridge PWM Output

        234
      • FIGURE 23-17: Example of Half-Bridge Applications

        234
    • 23.4.6 PWM Steering Mode

      235
      • FIGURE 23-18: Simplified Steering Block Diagram

        235
    • 23.4.7 Start-up Considerations

      236
      • FIGURE 23-19: Example of Steering Event at End of Instruction (STRxSYNC = 0)

        236
      • FIGURE 23-20: Example of Steering Event at Beginning of Instruction (STRxSYNC = 1)

        236
    • 23.4.8 Alternate Pin Locations

      237
      • TABLE 23-10: Summary of Registers Associated with Enhanced PWM

        237
  • 23.5 Register Definitions: ECCP Control

    238
    • Register 23-1: CCPXCON: CCPx Control Register

      238
    • Register 23-2: CCPTMRS0: PWM Timer Selection Control Register 0

      239
    • Register 23-3: CCPTMRS1: PWM Timer Selection Control Register 1

      239
    • Register 23-4: CCPxAS: CCPx Auto-Shutdown Control Register

      240
    • Register 23-5: PWMxCON: Enhanced PWM Control Register

      241
    • Register 23-6: PSTRxCON: PWM Steering Control Register(1)

      242
• 24.0 Master Synchronous Serial Port (MSSP1 and MSSP2) Module

  243
  • 24.1 Master SSPx (MSSPx) Module Overview

    243
    • FIGURE 24-1: MSSPx Block Diagram (SPI mode)

      243
    • FIGURE 24-2: MSSPx Block Diagram (I2C™ Master mode)

      244
    • FIGURE 24-3: MSSPx Block Diagram (I2C™ Slave mode)

      245
  • 24.2 SPI Mode Overview

    246
    • FIGURE 24-4: SPI Master and Multiple Slave Connection

      247
    • 24.2.1 SPI Mode Registers

      247
    • 24.2.2 SPI Mode Operation

      248
      • FIGURE 24-5: SPI Master/Slave Connection

        248
    • 24.2.3 SPI Master Mode

      249
      • FIGURE 24-6: SPI Mode Waveform (Master Mode)

        249
    • 24.2.4 SPI Slave Mode

      250
    • 24.2.5 Slave Select Synchronization

      250
      • FIGURE 24-7: SPI Daisy-Chain Connection

        251
      • FIGURE 24-8: slave Select Synchronous Waveform

        251
      • FIGURE 24-9: SPI Mode Waveform (Slave Mode With CKE = 0)

        252
      • FIGURE 24-10: SPI Mode Waveform (SLAve Mode With CKE = 1)

        252
    • 24.2.6 SPI Operation In Sleep Mode

      253
      • TABLE 24-1: Summary of Registers Associated with SPI Operation

        253
  • 24.3 I2C Mode Overview

    254
    • FIGURE 24-11: I2C Master/ Slave Connection

      254
    • 24.3.1 Clock Stretching

      255
    • 24.3.2 Arbitration

      255
  • 24.4 I2C Mode Operation

    255
    • 24.4.1 Byte Format

      255
    • 24.4.2 Definition of I2C Terminology

      255
    • 24.4.3 SDAx and SCLx PINS

      255
    • 24.4.4 SDAx Hold Time

      256
      • TABLE 24-2: I2C Bus terms

        256
    • 24.4.5 Start Condition

      257
    • 24.4.6 STOP Condition

      257
    • 24.4.7 Restart Condition

      257
    • 24.4.8 START/STOP Condition Interrupt masking

      257
      • FIGURE 24-12: I2C START and STOP Conditions

        257
      • FIGURE 24-13: I2C Restart Condition

        257
    • 24.4.9 Acknowledge Sequence

      258
  • 24.5 I2C Slave Mode Operation

    258
    • 24.5.1 Slave Mode Addresses

      258
    • 24.5.2 Slave Reception

      259
      • FIGURE 24-14: I2C Slave, 7-Bit Address, Reception (SEN = 0, AHEN = 0, DHEN = 0)

        260
      • FIGURE 24-15: I2C Slave, 7-Bit Address, Reception (SEN = 1, AHEN = 0, DHEN = 0)

        261
      • FIGURE 24-16: I2C Slave, 7-Bit Address, Reception (SEN = 0, AHEN = 1, DHEN = 1)

        262
      • FIGURE 24-17: I2C Slave, 7-Bit Address, Reception (SEN = 1, AHEN = 1, DHEN = 1)

        263
    • 24.5.3 SLAVE Transmission

      264
      • FIGURE 24-18: I2C Slave, 7-Bit Address, Transmission (AHEN = 0)

        265
      • FIGURE 24-19: I2C Slave, 7-Bit Address, Transmission (AHEN = 1)

        267
    • 24.5.4 Slave mode 10-bit Address Reception

      268
    • 24.5.5 10-bit Addressing With Address Or Data Hold

      268
      • FIGURE 24-20: I2C Slave, 10-Bit Address, Reception (SEN = 1, AHEN = 0, DHEN = 0)

        269
      • FIGURE 24-21: I2C Slave, 10-Bit Address, Reception (SeN = 0, AHEN = 1, DHEN = 0)

        270
      • FIGURE 24-22: I2C Slave, 10-Bit Address, Transmission (SEN = 0, AHEN = 0, DHEN = 0)

        271
    • 24.5.6 Clock Stretching

      272
    • 24.5.7 Clock Synchronization and the CKP Bit

      272
      • FIGURE 24-23: Clock Synchronization Timing

        272
    • 24.5.8 General Call Address Support

      273
      • FIGURE 24-24: Slave Mode General call address sequence

        273
    • 24.5.9 SSPx Mask Register

      273
  • 24.6 I2C Master Mode

    274
    • 24.6.1 I2C Master Mode Operation

      274
    • 24.6.2 Clock Arbitration

      275
      • FIGURE 24-25: Baud Rate Generator Timing with Clock Arbitration

        275
    • 24.6.3 WCOL Status Flag

      275
    • 24.6.4 I2C Master Mode Start Condition Timing

      276
      • FIGURE 24-26: First Start Bit Timing

        276
    • 24.6.5 I2C Master Mode Repeated Start Condition Timing

      277
      • FIGURE 24-27: Repeat Start Condition Waveform

        277
    • 24.6.6 I2C Master Mode Transmission

      278
      • FIGURE 24-28: I2C Master Mode Waveform (Transmission, 7 or 10-Bit Address)

        279
    • 24.6.7 I2C Master Mode Reception

      280
      • FIGURE 24-29: I2C Master Mode Waveform (Reception, 7-Bit Address)

        281
    • 24.6.8 Acknowledge Sequence Timing

      282
    • 24.6.9 Stop Condition Timing

      282
      • FIGURE 24-30: Acknowledge Sequence Waveform

        282
      • FIGURE 24-31: Stop Condition Receive or Transmit Mode

        283
    • 24.6.10 Sleep Operation

      283
    • 24.6.11 Effects of a Reset

      283
    • 24.6.12 Multi-Master Mode

      283
    • 24.6.13 Multi -Master Communication, Bus Collision and Bus Arbitration

      283
      • FIGURE 24-32: Bus Collision Timing for Transmit and Acknowledge

        284
      • FIGURE 24-33: Bus Collision During Start Condition (SDAx Only)

        285
      • FIGURE 24-34: Bus Collision During Start Condition (SCLx = 0)

        286
      • FIGURE 24-35: BRG Reset Due to Sda Arbitration During Start Condition

        286
      • FIGURE 24-36: Bus Collision During a Repeated Start Condition (Case 1)

        287
      • FIGURE 24-37: Bus Collision During Repeated Start Condition (Case 2)

        287
      • FIGURE 24-38: Bus Collision During a Stop Condition (Case 1)

        288
      • FIGURE 24-39: Bus Collision During a Stop Condition (Case 2)

        288
      • TABLE 24-3: Summary of Registers Associated with I2C™ Operation

        289
  • 24.7 Baud Rate Generator

    290
    • FIGURE 24-40: Baud Rate Generator Block Diagram

      290
    • TABLE 24-4: MSSPx Clock Rate w/BRG

      290
  • 24.8 Register Definitions: MSSP Control

    291
    • Register 24-1: SSPxSTAT: SSPx STATUS Register

      291
    • Register 24-2: SSPxCON1: SSPx Control Register 1

      292
    • Register 24-3: SSPxCON2: SSPx Control Register 2

      294
    • Register 24-4: SSPxCON3: SSPx Control Register 3

      295
    • Register 24-5: SSPxMSK: SSPx Mask Register

      296
    • Register 24-6: SSPxADD: MSSPx Address and Baud Rate Register (I2C Mode)

      296
• 25.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART)

  297
  • FIGURE 25-1: EUSART Transmit Block Diagram

    297
  • FIGURE 25-2: EUSART Receive Block Diagram

    298
  • 25.1 EUSART Asynchronous Mode

    299
    • 25.1.1 EUSART Asynchronous Transmitter

      299
      • FIGURE 25-3: Asynchronous Transmission

        300
      • FIGURE 25-4: Asynchronous Transmission (Back-to-Back)

        301
      • TABLE 25-1: Registers Associated with Asynchronous Transmission

        301
    • 25.1.2 EUSART Asynchronous Receiver

      302
      • FIGURE 25-5: Asynchronous Reception

        305
      • TABLE 25-2: Registers Associated with Asynchronous Reception

        305
  • 25.2 Clock Accuracy with Asynchronous Operation

    306
  • 25.3 Register Definitions: EUSART Control

    307
    • Register 25-1: TXxSTA: Transmit Status And Control Register

      307
    • Register 25-2: RCxSTA: Receive Status and Control Register

      308
    • Register 25-3: BAUDxCON: Baud Rate Control Register

      309
  • 25.4 EUSART Baud Rate Generator (BRG)

    310
    • EXAMPLE 25-1: Calculating Baud Rate Error

      310
    • TABLE 25-3: Baud Rate Formulas

      310
    • TABLE 25-4: Registers Associated with Baud Rate Generator

      311
    • TABLE 25-5: Baud Rates for Asynchronous Modes

      311
    • 25.4.1 Auto-Baud Detect

      314
      • TABLE 25-6: BRG Counter Clock Rates

        314
      • FIGURE 25-6: Automatic Baud Rate Calibration

        314
    • 25.4.2 Auto-baud Overflow

      315
    • 25.4.3 Auto-Wake-up on Break

      315
      • FIGURE 25-7: Auto-Wake-up Bit (WUE) Timing During Normal Operation

        316
      • FIGURE 25-8: Auto-Wake-up Bit (WUE) Timings During Sleep

        316
    • 25.4.4 Break Character Sequence

      317
    • 25.4.5 Receiving a Break Character

      317
      • FIGURE 25-9: Send Break Character Sequence

        317
  • 25.5 EUSART Synchronous Mode

    318
    • 25.5.1 Synchronous Master Mode

      318
      • FIGURE 25-10: Synchronous Transmission

        319
      • FIGURE 25-11: Synchronous Transmission (Through TXEN)

        319
      • TABLE 25-7: Registers Associated with Synchronous Master Transmission

        320
      • FIGURE 25-12: Synchronous Reception (Master Mode, SREN)

        322
      • TABLE 25-8: Registers Associated with Synchronous Master Reception

        322
    • 25.5.2 Synchronous Slave Mode

      323
      • TABLE 25-9: Registers Associated with Synchronous Slave Transmission

        324
      • TABLE 25-10: Registers Associated with Synchronous Slave Reception

        325
• 26.0 Capacitive Sensing (CPS) Module

  327
  • FIGURE 26-1: Capacitive Sensing Block Diagram

    327
  • FIGURE 26-2: Capacitive Sensing Oscillator Block Diagram

    328
  • 26.1 Analog MUX

    329
  • 26.2 Capacitive Sensing Oscillator

    329
    • 26.2.1 Voltage Reference Modes

      329
    • 26.2.2 Current Ranges

      330
      • TABLE 26-1: Power Mode Selection

        330
    • 26.2.3 Timer Resources

      330
    • 26.2.4 Fixed Time Base

      330
      • TABLE 26-2: Timer1 Enable Function

        331
    • 26.2.5 Software Control

      331
  • 26.3 Operation during Sleep

    332
  • 26.4 Register Definitions: Capacitive Sensing Control

    333
    • Register 26-1: CPSCON0: Capacitive Sensing Control Register 0

      333
    • Register 26-2: CPSCON1: Capacitive Sensing Control Register 1

      334
    • TABLE 26-3: Summary of Registers Associated with Capacitive Sensing

      334
• 27.0 Liquid Crystal Display (LCD) Driver Module

  335
  • 27.1 LCD Registers

    335
    • FIGURE 27-1: LCD Driver Module Block Diagram

      335
    • TABLE 27-1: LCD Segment and Data Registers

      336
  • 27.2 Register Definitions: Liquid Crystal Display (LCD) Control

    337
    • Register 27-1: LCDCON: Liquid Crystal Display (LCD) Control Register

      337
    • Register 27-2: LCDPS: LCD Phase Register

      338
    • Register 27-3: LCDREF: LCD Reference Voltage Control Register

      339
    • Register 27-4: LCDCST: LCD Contrast Control Register

      340
    • Register 27-5: LCDSEn: LCD Segment Enable Registers

      341
    • Register 27-6: LCDDATAn: LCD Data Registers

      341
  • 27.3 LCD Clock Source Selection

    342
    • 27.3.1 LCD Prescaler

      342
      • FIGURE 27-2: LCD Clock Generation

        342
  • 27.4 LCD Bias Voltage Generation

    343
    • TABLE 27-2: LCD Bias Voltages

      343
    • FIGURE 27-3: LCD Bias VOltage Generation Block DIagram

      343
  • 27.5 LCD Bias Internal Reference Ladder

    344
    • 27.5.1 Bias Mode Interaction

      344
      • TABLE 27-3: LCD Internal Ladder Power Modes (1/3 Bias)

        344
    • 27.5.2 Power Modes

      344
    • 27.5.3 Automatic power mode switching

      345
      • FIGURE 27-4: LCD Internal Reference Ladder Power Mode Switching Diagram – Type A

        345
      • FIGURE 27-5: LCD Internal Reference Ladder Power Mode Switching Diagram – Type A Waveform (1/2 Mux, 1/2 Bias Drive)

        346
      • FIGURE 27-6: LCD Internal Reference Ladder Power Mode Switching Diagram – Type B Waveform (1/2 Mux, 1/2 Bias Drive)

        347
  • 27.6 Register Definitions: LCD Ladder Control

    348
    • Register 27-7: LCDRL: LCD Reference Ladder Control Registers

      348
    • 27.6.1 Contrast Control

      349
      • FIGURE 27-7: Internal Reference and Contrast Control Block Diagram

        349
    • 27.6.2 Internal Reference

      349
    • 27.6.3 VLCD<3:1> pins

      349
  • 27.7 LCD Multiplex Types

    350
    • TABLE 27-4: Common Pin Usage

      350
  • 27.8 Segment Enables

    350
  • 27.9 Pixel Control

    350
  • 27.10 LCD Frame Frequency

    350
    • TABLE 27-5: Frame Frequency Formulas

      350
    • TABLE 27-6: Approximate Frame Frequency (in Hz) Using Fosc @ 8 MHz, Timer1 @ 32.768 kHz or LFINTOSC

      350
    • TABLE 27-7: LCD Segment Mapping Worksheet

      351
  • 27.11 LCD Waveform Generation

    352
    • FIGURE 27-8: Type-A/Type-B Waveforms in Static Drive

      352
    • FIGURE 27-9: Type-A Waveforms in 1/2 MUX, 1/2 Bias Drive

      353
    • FIGURE 27-10: Type-B Waveforms in 1/2 MUX, 1/2 Bias Drive

      354
    • FIGURE 27-11: Type-A Waveforms in 1/2 MUX, 1/3 Bias Drive

      355
    • FIGURE 27-12: Type-B Waveforms in 1/2 MUX, 1/3 Bias Drive

      356
    • FIGURE 27-13: Type-A Waveforms in 1/3 MUX, 1/2 Bias Drive

      357
    • FIGURE 27-14: Type-B Waveforms in 1/3 MUX, 1/2 Bias Drive

      358
    • FIGURE 27-15: Type-A Waveforms in 1/3 MUX, 1/3 Bias Drive

      359
    • FIGURE 27-16: Type-B Waveforms in 1/3 MUX, 1/3 Bias Drive

      360
    • FIGURE 27-17: Type-A Waveforms in 1/4 MUX, 1/3 Bias Drive

      361
    • FIGURE 27-18: Type-B Waveforms in 1/4 MUX, 1/3 Bias Drive

      362
  • 27.12 LCD Interrupts

    363
    • 27.12.1 LCD Interrupt on Module Shutdown

      363
    • 27.12.2 LCD Frame Interrupts

      363
      • FIGURE 27-19: Waveforms and Interrupt Timing in Quarter-Duty Cycle Drive (Example – Type-B, Non-Static)

        364
  • 27.13 Operation During Sleep

    365
    • TABLE 27-8: LCD Module Status During Sleep

      365
    • FIGURE 27-20: Sleep Entry/Exit when SLPEN = 1

      366
  • 27.14 Configuring the LCD Module

    367
  • 27.15 Disabling the LCD Module

    367
  • 27.16 LCD Current Consumption

    367
    • 27.16.1 Oscillator Selection

      367
    • 27.16.2 LCD Bias Source

      367
    • 27.16.3 Capacitance of the LCD segments

      367
      • TABLE 27-9: Summary of Registers Associated with LCD Operation

        368
• 28.0 In-Circuit Serial Programming™ (ICSP™)

  371
  • 28.1 High-Voltage Programming Entry Mode

    371
    • FIGURE 28-1: Vpp Limiter Example Circuit

      371
  • 28.2 Low-Voltage Programming Entry Mode

    372
  • 28.3 Common Programming Interfaces

    372
    • FIGURE 28-2: ICD RJ-11 Style Connector Interface

      372
    • FIGURE 28-3: PICkit™ Programmer Style Connector Interface

      372
    • FIGURE 28-4: Typical connection for ICSP™ programming

      373
• 29.0 Instruction Set Summary

  375
  • 29.1 Read-Modify-Write Operations

    375
    • TABLE 29-1: Opcode Field Descriptions

      375
    • TABLE 29-2: Abbreviation Descriptions

      375
    • FIGURE 29-1: General Format for Instructions

      376
    • TABLE 29-3: PIC16(L)F1946/47 Instruction Set

      377
    • TABLE 29-3: PIC16(L)F1946/47 Enhanced Instruction Set (Continued)

      378
  • 29.2 Instruction Descriptions

    379
• 30.0 Electrical Specifications

  389
  • Absolute Maximum Ratings(†)

    389
    • FIGURE 30-1: PIC16F1946/47 Voltage Frequency Graph, -40°C £ Ta £ +125°C

      390
    • FIGURE 30-2: PIC16LF1946/47 Voltage Frequency Graph, -40°C £ Ta £ +125°C

      390
    • FIGURE 30-3: HFINTOSC Frequency Accuracy Over Device Vdd and Temperature

      391
  • 30.1 DC Characteristics: PIC16(L)F1946/47-I/E (Industrial, Extended)

    392
    • FIGURE 30-4: POR and POR Rearm with Slow Rising Vdd

      393
  • 30.2 DC Characteristics: PIC16(L)F1946/47-I/E (Industrial, Extended)

    394
  • 30.3 DC Characteristics: PIC16(L)F1946/47-I/E (Power-Down)

    397
  • 30.4 DC Characteristics: PIC16(L)F1946/47-I/E

    400
  • 30.5 Memory Programming Requirements

    401
  • 30.6 Thermal Considerations

    402
  • 30.7 Timing Parameter Symbology

    403
    • FIGURE 30-5: Load Conditions

      403
  • 30.8 AC Characteristics: PIC16(L)F1946/47-I/E

    404
    • FIGURE 30-6: Clock Timing

      404
    • TABLE 30-1: Clock Oscillator Timing Requirements

      404
    • TABLE 30-2: Oscillator Parameters

      405
    • TABLE 30-3: PLL Clock Timing Specifications (Vdd = 2.7V to 5.5V)

      405
    • FIGURE 30-7: CLKOUT and I/O Timing

      405
    • TABLE 30-4: CLKOUT and I/O Timing Parameters

      406
    • FIGURE 30-8: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing

      406
    • FIGURE 30-9: Brown-Out Reset Timing and Characteristics

      407
    • TABLE 30-5: Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and Brown-Out Reset Parameters

      408
    • FIGURE 30-10: Timer0 and Timer1 External Clock Timings

      408
    • TABLE 30-6: Timer0 and Timer1 External Clock Requirements

      409
    • FIGURE 30-11: Capture/Compare/PWM Timings (CCP)

      409
    • TABLE 30-7: Capture/Compare/PWM Requirements (CCP)

      409
    • TABLE 30-8: PIC16(L)F1946/47 A/D Converter (ADC) Characteristics(1,2,3):

      410
    • TABLE 30-9: PIC16(L)F1946/47 A/D Conversion Requirements

      410
    • FIGURE 30-12: PIC16(L)F1946/47 A/D Conversion Timing (Normal Mode)

      411
    • FIGURE 30-13: PIC16(L)F1946/47 A/D Conversion Timing (Sleep Mode)

      411
    • TABLE 30-10: Comparator Specifications

      412
    • TABLE 30-11: Digital-to-Analog Converter (DAC) Specifications

      412
    • FIGURE 30-14: USART Synchronous Transmission (Master/Slave) Timing

      412
    • TABLE 30-12: USART Synchronous Transmission Requirements

      413
    • FIGURE 30-15: USART Synchronous Receive (Master/Slave) Timing

      413
    • TABLE 30-13: USART Synchronous Receive Requirements

      413
    • FIGURE 30-16: SPI Master Mode Timing (CKE = 0, SMP = 0)

      414
    • FIGURE 30-17: SPI Master Mode Timing (CKE = 1, SMP = 1)

      414
    • FIGURE 30-18: SPI Slave Mode Timing (CKE = 0)

      415
    • FIGURE 30-19: SPI Slave Mode Timing (CKE = 1)

      415
    • TABLE 30-14: SPI Mode requirements

      416
    • FIGURE 30-20: I2C™ Bus Start/Stop Bits Timing

      416
    • TABLE 30-15: I2C™ Bus Start/Stop Bits Requirements

      417
    • FIGURE 30-21: I2C™ Bus Data Timing

      417
    • TABLE 30-16: I2C™ Bus Data Requirements

      418
    • TABLE 30-17: Cap Sense Oscillator Specifications

      419
    • FIGURE 30-22: Cap Sense Oscillator

      419
• 31.0 DC and AC Characteristics Graphs and Charts

  421
  • FIGURE 31-1: Idd, LP Oscillator Mode, Fosc = 32 kHz, PIC16LF1946/47 Only

    422
  • FIGURE 31-2: Idd, LP Oscillator Mode, Fosc = 32 kHz, PIC16F1946/47 only

    422
  • FIGURE 31-3: Idd Typical, XT and EXTRC Oscillator, PIC16LF1946/47 only

    423
  • FIGURE 31-4: Idd Maximum, XT and EXTRC Oscillator, PIC16LF1946/47 only

    423
  • FIGURE 31-5: Idd Typical, XT and EXTRC Oscillator, PIC16F1946/47 only

    424
  • FIGURE 31-6: Idd Maximum, XT and EXTRC Oscillator, PIC16F1946/47 only

    424
  • FIGURE 31-7: Idd, EC Oscillator, Low-Power Mode, Fosc = 32 kHz, PIC16LF1946/47 only

    425
  • FIGURE 31-8: Idd, EC Oscillator, Low-Power Mode, Fosc = 32 kHz, PIC16F1946/47 only

    425
  • FIGURE 31-9: Idd, EC Oscillator, Low-Power Mode, Fosc = 500 kHz, PIC16LF1946/47 only

    426
  • FIGURE 31-10: Idd, EC Oscillator, Low-Power Mode, Fosc = 500 kHz, PIC16F1946/47 only

    426
  • FIGURE 31-11: Idd Typical, EC Oscillator, Medium-Power Mode, PIC16LF1946/47 only

    427
  • FIGURE 31-12: Idd Maximum, EC Oscillator, Medium-Power Mode, PIC16LF1946/47 only

    427
  • FIGURE 31-13: Idd Typical, EC Oscillator, Medium-Power Mode, PIC16F1946/47 only

    428
  • FIGURE 31-14: Idd Maximum, EC Oscillator, Medium-Power Mode, PIC16F1946/47 only

    428
  • FIGURE 31-15: Idd Typical, EC Oscillator, High-Power Mode, PIC16LF1946/47 only

    429
  • FIGURE 31-16: Idd Maximum, EC Oscillator, High-Power Mode, PIC16LF1946/47 only

    429
  • FIGURE 31-17: Idd Typical, EC Oscillator, High-Power Mode, PIC16F1946/47 only

    430
  • FIGURE 31-18: Idd Maximum, EC Oscillator, High-Power Mode, PIC16F1946/47 only

    430
  • FIGURE 31-19: Idd, LFINTOSC Mode, Fosc = 32 kHz, PIC16LF1946/47 only

    431
  • FIGURE 31-20: Idd, LFINTOSC Mode, Fosc = 32 kHz, PIC16F1946/47 only

    431
  • FIGURE 31-21: Idd, MFINTOSC Mode, Fosc = 500 kHz, PIC16LF1946/47 only

    432
  • FIGURE 31-22: Idd, MFINTOSC Mode, Fosc = 500 kHz, PIC16F1946/47 only

    432
  • FIGURE 31-23: Idd Typical, HFINTOSC Mode, PIC16LF1946/47 only

    433
  • FIGURE 31-24: Idd Maximum, HFINTOSC Mode, PIC16LF1946/47 only

    433
  • FIGURE 31-25: Idd Typical, HFINTOSC Mode, PIC16F1946/47 only

    434
  • FIGURE 31-26: Idd Maximum, HFINTOSC Mode, PIC16F1946/47 only

    434
  • FIGURE 31-27: Idd Typical, HS Oscillator, PIC16LF1946/47 only

    435
  • FIGURE 31-28: Idd Maximum, HS Oscillator, PIC16LF1946/47 only

    435
  • FIGURE 31-29: Idd Typical, HS Oscillator, PIC16F1946/47 only

    436
  • FIGURE 31-30: Idd Maximum, HS Oscillator, PIC16F1946/47 only

    436
  • FIGURE 31-31: Ipd Base, PIC16LF1946/47 only

    437
  • FIGURE 31-32: Ipd Base, PIC16F1946/47 only

    437
  • FIGURE 31-33: Ipd, Watchdog Timer (WDT), PIC16LF1946/47 only

    438
  • FIGURE 31-34: Ipd, Watchdog Timer (WDT), PIC16F1946/47 only

    438
  • FIGURE 31-35: Ipd, Fixed Voltage Reference (FVR), PIC16LF1946/47 only

    439
  • FIGURE 31-36: Ipd, Fixed Voltage Reference (FVR), PIC16F1946/47 only

    439
  • FIGURE 31-37: Ipd, Brown-Out Reset (BOR), PIC16LF1946/47 only

    440
  • FIGURE 31-38: Ipd, Brown-Out Reset (BOR), PIC16F1946/47 only

    440
  • FIGURE 31-39: Ipd, Timer1 Oscillator, Fosc = 32 kHz, PIC16LF1946/47 only

    441
  • FIGURE 31-40: Ipd, Timer1 Oscillator, Fosc = 32 kHz, PIC16F1946/47 only

    441
  • FIGURE 31-41: Ipd, Capacitive Sensing (CPS) Module, Low-Current Range, CPSRM = 0, PIC16LF1946/47 only

    442
  • FIGURE 31-42: Ipd, Capacitive Sensing (CPS) Module, Low-Current Range, CPSRM = 0, PIC16F1946/47 only

    442
  • FIGURE 31-43: Ipd, Capacitive Sensing (CPS) Module, Medium-Current Range, CPSRM = 0, PIC16LF1946/47 only

    443
  • FIGURE 31-44: Ipd, Capacitive Sensing (CPS) Module, Medium-Current Range, CPSRM = 0, PIC16F1946/47 only

    443
  • FIGURE 31-45: Ipd, Capacitive Sensing (CPS) Module, High-Current Range, CPSRM = 0, PIC16LF1946/47 only

    444
  • FIGURE 31-46: Ipd, Capacitive Sensing (CPS) Module, High-Current Range, CPSRM = 0, PIC16F1946/47 only

    444
  • FIGURE 31-47: Ipd, Comparator, Low-Power Mode, PIC16LF1946/47 only

    445
  • FIGURE 31-48: Ipd, Comparator, Low-Power Mode, PIC16F1946/47 only

    445
  • FIGURE 31-49: Ipd, Comparator, High-Power Mode, PIC16LF1946/47 only

    446
  • FIGURE 31-50: Ipd, Comparator, High-Power Mode, PIC16F1946/47 only

    446
  • FIGURE 31-51: Voh vs. Ioh Over Temperature, Vdd = 5.0V, PIC16F1946/47 only

    447
  • FIGURE 31-52: Vol vs. Iol Over Temperature, Vdd = 5.0V, PIC16F1946/47 only

    447
  • FIGURE 31-53: Voh vs. Ioh Over Temperature, Vdd = 3.0V

    448
  • FIGURE 31-54: Vol vs. Iol Over Temperature, Vdd = 3.0V

    448
  • FIGURE 31-55: Voh vs. Ioh Over Temperature, Vdd = 1.8V

    449
  • FIGURE 31-56: Vol vs. Iol Over Temperature, Vdd = 1.8V

    449
  • FIGURE 31-57: Brown-out Reset Voltage, BORV = 1

    450
  • FIGURE 31-58: Brown-out Reset Hysteresis, BORV = 1

    450
  • FIGURE 31-59: Brown-out Reset Voltage, BORV = 0

    451
  • FIGURE 31-60: Brown-out Reset Hysteresis, BORV = 0

    451
  • FIGURE 31-61: Comparator Hysteresis, High-Power Mode

    452
  • FIGURE 31-62: Comparator Hysteresis, Low-Power Mode

    452
  • FIGURE 31-63: Comparator Response Time, High-Power Mode

    453
  • FIGURE 31-64: Comparator Response Time Over Temperature, High-Power Mode

    453
  • FIGURE 31-65: Comparator Input Offset at 25°C, High-Power Mode, PIC16F1946/47 only

    454
  • 32.0 Development Support

    455
• 33.0 Packaging Information

  459
  • 33.1 Package Marking Information

    459
  • 33.2 Package Details

    460
• Appendix A: Data Sheet Revision History

  465
  • Revision A (3/2010)

    465
  • Revision B (9/2010)

    465
  • Revision C (5/2011)

    465
  • Revision D (02/2012)

    465
• Appendix B: Migrating From Other PIC® Devices

  465
  • TABLE B-1: Feature Comparison

    465
• INDEX

  467
• The Microchip Web Site

  475
• Customer Change Notification Service

  475
• Customer Support

  475
• Reader Response

  476
• Product Identification System

  477
• Worldwide Sales

  478