Scheda TecnicaSommarioTable of Contents5Preface7Introduction7Document Layout8Conventions Used in this Guide9Warranty Registration10Recommended Reading10The Microchip Web Site11Development Systems Customer Change Notification Service11Customer Support12Revision History12Chapter 1. Introduction to the Starter Kit131.1 Overview131.2 What’s in the Kit141.3 Hardware14Figure 1-1: Starter Kit Board, front and back views14Table 1-1: Mapping of Breakout Connector pins to Microcontroller Functions171.3.1 Power Sources181.3.1.1 SWITCHED_VDD Control181.4 Installing Device Drivers for the Starter Kit18Chapter 2. The Demonstration Application192.1 Start-up Display192.2 Sections of the Demo192.2.1 Clock Demo202.2.2 Sigma-Delta A/D Demo202.2.3 Pipeline A/D Demo212.2.4 Stereo DAC Demo212.2.5 TC77 Temperature Sensor Demo212.2.6 LCD Test Demo212.2.7 Audio/Microphone Demo222.2.8 Background Data Transmission222.2.9 Entering Reduced Power (Sleep) Mode222.3 Other Hardware Resources on the Starter Kit23Chapter 3. Developing New Applications253.1 Reprogramming the Starter Kit Using the PKOB25Figure 3-1: Selecting the PKOB in Earlier Versions of MPLAB® IDE25Figure 3-2: Selecting the PKOB263.2 Hardware Considerations for New Applications27Table 3-1: I/O Pins Available for User27Chapter 4. Troubleshooting29Appendix A. Starter Kit Schematics31Figure A-1: Starter Kit, Sheet 1 (PIC24FJ128GC010 Microcontroller)32Figure A-2: Starter Kit, Sheet 2 (Other Front-side Circuits)33Figure A-3: Starter Kit, sheet 3 (PICkit™ on Board Programmer)34Appendix B. LCD Panel Information35Figure B-1: Microchip Custom LCD Panel (Element Numbers shown in Grey)35Table B-1: LCD Panel Pin Mapping36Table B-2: LCD Panel Display Element Mapping37Appendix C. Optional Microphone Amplifier39Figure C-1: Microphone Amplifier schematic39Table C-1: Microphone Amplifier Component List39Index41Worldwide Sales and Service42Dimensioni: 1,03 MBPagine: 42Language: EnglishApri il manuale
Scheda TecnicaSommarioAdvanced Analog Features1Extreme Low-Power Features1Universal Serial Bus Features2Peripheral Features2High-Performance CPU2Special Microcontroller Features2Pin Diagrams3Pin Diagrams (Continued)5Pin Diagrams (Continued)8Table of Contents11Most Current Data Sheet12Errata12Customer Notification System121.0 Device Overview131.1 Core Features131.1.1 16-Bit Architecture131.1.2 XLP Power-Saving Technology131.1.3 Oscillator Options and Features131.1.4 Easy Migration131.2 Advanced Analog Features141.3 DMA Controller141.4 USB On-The-Go (OTG)141.5 LCD Controller141.6 Other Special Features151.7 Details on Individual Family Members15TABLE 1-1: Device Features for the PIC24FJ128GC010 family: 64-pin16TABLE 1-2: Device Features for the PIC24FJ128GC010 family: 100/121-pin Devices17FIGURE 1-1: PIC24FJ128GC010 family General Block Diagram18TABLE 1-3: PIC24FJ128GC010 family Pinout Description192.0 Guidelines for Getting Started with 16-Bit Microcontrollers332.1 Basic Connection Requirements33FIGURE 2-1: Recommended Minimum connections332.2 Power Supply Pins342.2.1 Decoupling Capacitors342.2.2 Bulk Capacitors342.3 Master Clear (MCLR) Pin34FIGURE 2-2: Example of MCLR Pin Connections342.4 Voltage Regulator Pin (Vcap)35FIGURE 2-3: Frequency vs. ESR Performance for Suggested Vcap35TABLE 2-1: Suitable Capacitor Equivalents352.4.1 Considerations for Ceramic Capacitors36FIGURE 2-4: DC Bias Voltage vs. Capacitance Characteristics362.5 ICSP Pins362.6 External Oscillator Pins37FIGURE 2-5: Suggested Placement of the Oscillator Circuit372.7 Configuration of Analog and Digital Pins During ICSP Operations382.8 Sigma-Delta A/D Connections382.8.1 Voltage and ground Connections382.8.2 ANALOG Inputs382.9 Unused I/Os383.0 CPU393.1 Programmer’s Model39FIGURE 3-1: PIC24F CPU Core Block Diagram40TABLE 3-1: CPU Core Registers40FIGURE 3-2: Programmer’s Model413.2 CPU Control Registers42Register 3-1: SR: ALU STATUS Register42Register 3-2: CORCON: CPU Core Control Register433.3 Arithmetic Logic Unit (ALU)443.3.1 Multiplier443.3.2 Divider443.3.3 Multibit Shift Support44TABLE 3-2: Instructions that Use the Single Bit and Multibit Shift Operation444.0 Memory Organization454.1 Program Memory Space45FIGURE 4-1: Program Space Memory Map for PIC24FJ128GC010 family Devices454.1.1 Program Memory Organization464.1.2 Hard Memory Vectors464.1.3 Flash Configuration Words46TABLE 4-1: Flash Configuration Words for PIC24FJ128GC010 family Devices46FIGURE 4-2: Program Memory Organization464.2 Data Memory Space474.2.1 Data Space Width47FIGURE 4-3: Data Space Memory Map for PIC24FJ128GC010 family Devices474.2.2 Data Memory Organization and Alignment484.2.3 Near Data Space484.2.4 Special Function Register (SFR) Space48TABLE 4-2: Implemented Regions of SFR Data Space48TABLE 4-3: CPU CORE Registers Map49TABLE 4-4: ICN Register Map50TABLE 4-5: Interrupt Controller Register Map51TABLE 4-6: Timer Register Map52TABLE 4-7: Input Capture Register Map53TABLE 4-8: Output Compare Register Map54TABLE 4-9: I2C™ Register Map55TABLE 4-10: UART Register Maps56TABLE 4-11: SPI Register Map56TABLE 4-12: Op Amp Register Map57TABLE 4-13: PORTA Register Map(1)57TABLE 4-14: PORTb Register Map57TABLE 4-15: PORTC Register Map58TABLE 4-16: PORTD Register Map58TABLE 4-17: PORTE Register Map58TABLE 4-18: PORTF Register Map59TABLE 4-19: PORTG Register Map59TABLE 4-20: Pad Configuration Register Map (PADCFG1)59TABLE 4-21: CTMU Register Map59TABLE 4-22: DAC Register Map60TABLE 4-23: Sigma-Delta A/D Register Map60TABLE 4-24: Analog Configuration Register Map60TABLE 4-25: 12-Bit Pipeline A/D Converter Register Map61TABLE 4-26: DMA Register Map65TABLE 4-27: USB OTG Register Map66TABLE 4-28: LCD Controller Register Map67TABLE 4-29: Parallel Master/Slave Port Register Map69TABLE 4-30: Real-Time Clock and Calendar (RTCC) Register Map69TABLE 4-31: Data Signal Modulator (DSM) Register Map69TABLE 4-32: Comparators Register Map70TABLE 4-33: CRC Register Map70TABLE 4-34: Band Gap Buffer Interface Register Map70TABLE 4-35: Peripheral Pin Select Register Map71TABLE 4-36: System Control (Clock and Reset) Register Map72TABLE 4-37: Deep Sleep Register Map73TABLE 4-38: NVM Register Map73TABLE 4-39: PMD Register Map734.2.5 Extended Data Space (EDS)74TABLE 4-40: Total Accessible Data Memory74FIGURE 4-4: Extended Data Space74FIGURE 4-5: EDS Address Generation for Read Operations75EXAMPLE 4-1: EDS Read Code In Assembly75FIGURE 4-6: EDS Address Generation for Write Operations76EXAMPLE 4-2: EDS Write Code In Assembly76TABLE 4-41: EDS Memory Address with Different Pages and Addresses774.2.6 Software Stack77FIGURE 4-7: CALL Stack Frame774.3 Interfacing Program and Data Memory Spaces784.3.1 Addressing Program Space78TABLE 4-42: Program Space Address Construction78FIGURE 4-8: Data Access from Program Space Address Generation794.3.2 Data Access from Program Memory Using Table Instructions80FIGURE 4-9: Accessing Program Memory with Table Instructions804.3.3 Reading Data from Program Memory Using EDS81TABLE 4-43: EDS Program Address with different Pages and Addresses81EXAMPLE 4-3: EDS Read Code from Program Memory In Assembly81FIGURE 4-10: Program Space Visibility Operation to Access Lower Word82FIGURE 4-11: Program Space Visibility Operation to Access Upper Word825.0 Direct Memory Access Controller (DMA)83FIGURE 5-1: DMA Controller Functional Block Diagram835.1 Summary of DMA Operations845.1.1 Source and Destination845.1.2 Data Size845.1.3 Trigger Source845.1.4 Transfer Mode845.1.5 Addressing Modes84FIGURE 5-2: Types of DMA Data Transfers855.1.6 Channel Priority865.2 Typical Setup865.3 Peripheral Module Disable865.4 Registers86Register 5-1: DMACON: DMA Engine Control Register87Register 5-2: DMACHn: DMA Channel n Control Register88Register 5-3: DMAINTn: DMA Channel n Interrupt Register89TABLE 5-1: DMA Trigger Sources906.0 Flash Program Memory916.1 Table Instructions and Flash Programming91FIGURE 6-1: Addressing for Table Registers916.2 RTSP Operation926.3 Enhanced In-Circuit Serial Programming926.4 Control Registers92Register 6-1: NVMCON: Flash Memory Control Register936.5 Programming Operations946.5.1 Programming Algorithm for Flash Program Memory94EXAMPLE 6-1: Erasing a Program Memory Block (Assembly Language Code)94EXAMPLE 6-2: Erasing a Program Memory Block (‘C’ Language Code)95EXAMPLE 6-3: LOADING THE WRITE BUFFERS95EXAMPLE 6-4: Initiating a Programming Sequence956.5.2 Programming a single word of flash program memory96EXAMPLE 6-5: Programming a Single Word of Flash Program Memory96EXAMPLE 6-6: Programming a Single Word of Flash Program Memory (‘C’ Language Code)967.0 Resets97FIGURE 7-1: Reset System Block Diagram97Register 7-1: RCON: Reset Control Register98Register 7-2: RCON2: Reset and System Control Register 2100TABLE 7-1: Reset Flag Bit Operation1007.1 Special Function Register Reset States1017.2 Device Reset Times1017.3 Brown-out Reset (BOR)1017.4 Clock Source Selection at Reset101TABLE 7-2: Oscillator Selection vs. Type of Reset (Clock Switching Enabled)101TABLE 7-3: Reset Delay Times for Various Device Resets1027.4.1 POR and Long Oscillator Start-up Times1027.4.2 Fail-Safe Clock Monitor (FSCM) and Device Resets1028.0 Interrupt Controller1038.1 Interrupt Vector Table1038.1.1 Alternate Interrupt Vector Table1038.2 Reset Sequence103FIGURE 8-1: PIC24F Interrupt Vector Table104TABLE 8-1: Trap Vector Details104TABLE 8-2: Implemented Interrupt Vectors1058.3 Interrupt Control and Status Registers107Register 8-1: SR: ALU STATUS Register (in CPU)108Register 8-2: CORCON: CPU Control Register109Register 8-3: INTCON1: Interrupt Control Register 1110Register 8-4: INTCON2: Interrupt Control Register 2111Register 8-5: IFS0: Interrupt Flag Status Register 0112Register 8-6: IFS1: Interrupt Flag Status Register 1114Register 8-7: IFS2: Interrupt Flag Status Register 2116Register 8-8: IFS3: Interrupt Flag Status Register 3117Register 8-9: IFS4: Interrupt Flag Status Register 4118Register 8-10: IFS5: Interrupt Flag Status Register 5119Register 8-11: IFS6: Interrupt Flag Status Register 6120Register 8-12: IFS7: Interrupt Flag Status Register 7121Register 8-13: IEC0: Interrupt Enable Control Register 0122Register 8-14: IEC1: Interrupt Enable Control Register 1124Register 8-15: IEC2: Interrupt Enable Control Register 2126Register 8-16: IEC3: Interrupt Enable Control Register 3127Register 8-17: IEC4: Interrupt Enable Control Register 4128Register 8-18: IEC5: Interrupt Enable Control Register 5129Register 8-19: IEC6: Interrupt Enable Control Register 6130Register 8-20: IEC7: Interrupt Enable Control Register 7131Register 8-21: IPC0: Interrupt Priority Control Register 0132Register 8-22: IPC1: Interrupt Priority Control Register 1133Register 8-23: IPC2: Interrupt Priority Control Register 2134Register 8-24: IPC3: Interrupt Priority Control Register 3135Register 8-25: IPC4: Interrupt Priority Control Register 4136Register 8-26: IPC5: Interrupt Priority Control Register 5137Register 8-27: IPC6: Interrupt Priority Control Register 6138Register 8-28: IPC7: Interrupt Priority Control Register 7139Register 8-29: IPC8: Interrupt Priority Control Register 8140Register 8-30: IPC9: Interrupt Priority Control Register 9141Register 8-31: IPC10: Interrupt Priority Control Register 10142Register 8-32: IPC11: Interrupt Priority Control Register 11143Register 8-33: IPC12: Interrupt Priority Control Register 12144Register 8-34: IPC13: Interrupt Priority Control Register 13145Register 8-35: IPC15: Interrupt Priority Control Register 15146Register 8-36: IPC16: Interrupt Priority Control Register 16147Register 8-37: IPC18: Interrupt Priority Control Register 18148Register 8-38: IPC19: Interrupt Priority Control Register 19149Register 8-39: IPC20: Interrupt Priority Control Register 20150Register 8-40: IPC21: Interrupt Priority Control Register 21151Register 8-41: IPC22: Interrupt Priority Control Register 22152Register 8-42: IPC23: Interrupt Priority Control Register 23153Register 8-43: IPC25: Interrupt Priority Control Register 25154Register 8-44: IPC26: Interrupt Priority Control Register 26155Register 8-45: IPC29: Interrupt Priority Control Register 29156Register 8-46: INTTREG: Interrupt Controller Test Register1578.4 Interrupt Setup Procedures1588.4.1 Initialization1588.4.2 Interrupt Service Routine (ISR)1588.4.3 Trap Service Routine (TSR)1588.4.4 Interrupt Disable1589.0 Oscillator Configuration159FIGURE 9-1: PIC24FJ128GC010 family Clock Diagram1599.1 CPU Clocking Scheme1609.2 Initial Configuration on POR1609.2.1 Clock Switching Mode Configuration Bits160TABLE 9-1: Configuration Bit Values for Clock Selection1609.3 Control Registers161Register 9-1: OSCCON: Oscillator Control Register161Register 9-2: CLKDIV: Clock Divider Register163Register 9-3: OSCTUN: FRC Oscillator Tune Register1649.4 Clock Switching Operation1659.4.1 Enabling Clock Switching1659.4.2 Oscillator Switching Sequence165EXAMPLE 9-1: Basic Code Sequence for Clock Switching1669.5 FRC Active Clock Tuning1669.6 Oscillator Modes and USB Operation167TABLE 9-2: System Clock Options During USB Operation167TABLE 9-3: Valid Primary Oscillator Configurations for USB Operations167FIGURE 9-2: PLL Block1679.6.1 Considerations for USB Operation1689.7 Reference Clock Output1689.8 Secondary Oscillator1689.8.1 Basic SOSC Operation1689.8.2 Crystal Selection168Register 9-4: REFOCON: Reference Oscillator Control Register16910.0 Power-Saving Features17110.1 Overview of Power-Saving Modes171TABLE 10-1: Operating Modes for PIC24FJ128GC010 family Devices171TABLE 10-2: Exiting Power Saving Modes17210.1.1 Instruction-Based Power-Saving Modes172EXAMPLE 10-1: PWRSAV Instruction Syntax17210.1.2 Hardware-Based Power-Saving Mode17310.1.3 Low-Voltage/Retention Regulator17310.2 Idle Mode17310.3 Sleep Mode17310.3.1 Low-Voltage/Retention Sleep Mode17310.4 Deep Sleep Mode17410.4.1 Retention Deep Sleep17410.4.2 Entering Deep Sleep Mode174EXAMPLE 10-2: The Repeat Sequence17510.4.3 Exiting Deep Sleep Modes17510.4.4 Saving Context Data with the DSGPRx Registers17510.4.5 I/O Pins in Deep Sleep Modes17510.4.6 Deep Sleep WDT17610.4.7 Checking and Clearing the Status of Deep Sleep17610.4.8 Power-on Resets (PORs)17610.5 Vbat Mode17710.5.1 Vbat mode with no RTCC17710.5.2 WAKE-UP FROM Vbat modes17710.5.3 I/O PINS DURING Vbat modes17710.5.4 Saving Context Data with the DSGPRx Registers177Register 10-1: DSCON: Deep Sleep Control Register(1)178Register 10-2: DSWAKE: Deep Sleep Wake-Up Source Register(1)179Register 10-3: RCON2: Reset and System Control Register 218010.6 Clock Frequency and Clock Switching18110.7 Doze Mode18110.8 Selective Peripheral Module Control18111.0 I/O Ports18311.1 Parallel I/O (PIO) Ports183FIGURE 11-1: Block Diagram of a Typical Shared Port Structure18311.1.1 I/O Port Write/Read Timing18411.1.2 Open-Drain Configuration18411.1.3 GPIO Functions on the USB Pins18411.2 Configuring Analog Port Pins (ANSx)18411.2.1 Analog Input Pins and Voltage Considerations184TABLE 11-1: Configuring Analog/Digital Function of an I/O Pin184TABLE 11-2: Input Voltage Levels for Port or Pin Tolerated Description Input185Register 11-1: ANSA: PortA Analog Function Selection Register186Register 11-2: ANSB: PortB Analog Function Selection Register187Register 11-3: ANSC: PortC Analog Function Selection Register187Register 11-4: ANSD: PortD Analog Function Selection Register188Register 11-5: ANSE: PORTE Analog Function Selection Register(1)188Register 11-6: ANSF: PortF Analog Function Selection Register189Register 11-7: ANSG: PortG Analog Function Selection Register19011.3 Input Change Notification (ICN)191EXAMPLE 11-1: Port Write/Read in Assembly191EXAMPLE 11-2: Port Write/Read in ‘C’19111.4 Peripheral Pin Select (PPS)19211.4.1 Available Pins19211.4.2 Available Peripherals19211.4.3 Controlling Peripheral Pin Select192TABLE 11-3: Selectable Input Sources (Maps Input to Function)(1)193TABLE 11-4: Selectable Output Sources (Maps Function to Output)19411.4.4 Controlling Configuration Changes195TABLE 11-5: Remappable Pin Exceptions for PIC24FJ128GC010 family Devices19511.4.5 Considerations for Peripheral Pin Selection196EXAMPLE 11-3: Configuring UART1 Input and Output Functions19611.4.6 Peripheral Pin Select Registers197Register 11-8: RPINR0: Peripheral Pin Select Input Register 0197Register 11-9: RPINR1: Peripheral Pin Select Input Register 1197Register 11-10: RPINR2: Peripheral Pin Select Input Register 2198Register 11-11: RPINR7: Peripheral Pin Select Input Register 7198Register 11-12: RPINR8: Peripheral Pin Select Input Register 8199Register 11-13: RPINR9: Peripheral Pin Select Input Register 9199Register 11-14: RPINR10: Peripheral Pin Select Input Register 10200Register 11-15: RPINR11: Peripheral Pin Select Input Register 11200Register 11-16: RPINR15: Peripheral Pin Select Input Register 15201Register 11-17: RPINR17: Peripheral Pin Select Input Register 17201Register 11-18: RPINR18: Peripheral Pin Select Input Register 18202Register 11-19: RPINR19: Peripheral Pin Select Input Register 19202Register 11-20: RPINR20: Peripheral Pin Select Input Register 20203Register 11-21: RPINR21: Peripheral Pin Select Input Register 21203Register 11-22: RPINR22: Peripheral Pin Select Input Register 22204Register 11-23: RPINR23: Peripheral Pin Select Input Register 23204Register 11-24: RPINR27: Peripheral Pin Select Input Register 27205Register 11-25: RPINR30: Peripheral Pin Select Input Register 30205Register 11-26: RPINR31: Peripheral Pin Select Input Register 31206Register 11-27: RPOR0: Peripheral Pin Select Output Register 0207Register 11-28: RPOR1: Peripheral Pin Select Output Register 1207Register 11-29: RPOR2: Peripheral Pin Select Output Register 2208Register 11-30: RPOR3: Peripheral Pin Select Output Register 3208Register 11-31: RPOR4: Peripheral Pin Select Output Register 4209Register 11-32: RPOR5: Peripheral Pin Select Output Register 5209Register 11-33: RPOR6: Peripheral Pin Select Output Register 6210Register 11-34: RPOR7: Peripheral Pin Select Output Register 7210Register 11-35: RPOR8: Peripheral Pin Select Output Register 8211Register 11-36: RPOR9: Peripheral Pin Select Output Register 9211Register 11-37: RPOR10: Peripheral Pin Select Output Register 10212Register 11-38: RPOR11: Peripheral Pin Select Output Register 11212Register 11-39: RPOR12: Peripheral Pin Select Output Register 12213Register 11-40: RPOR13: Peripheral Pin Select Output Register 13213Register 11-41: RPOR14: Peripheral Pin Select Output Register 14214Register 11-42: RPOR15: Peripheral Pin Select Output Register 1521412.0 Timer1215FIGURE 12-1: 16-bit Timer1 Module Block Diagram215Register 12-1: T1CON: Timer1 Control Register(1)21613.0 Timer2/3 and Timer4/5217FIGURE 13-1: Timer2/3 and Timer4/5 (32-bit) Block Diagram218FIGURE 13-2: Timer2 and Timer4 (16-bit Synchronous) Block Diagram219FIGURE 13-3: Timer3 and Timer5 (16-bit Asynchronous) Block Diagram219Register 13-1: TxCON: Timer2 and Timer4 Control Register(1)220Register 13-2: TyCON: Timer3 and Timer5 Control Register(1)22214.0 Input Capture with Dedicated Timers22314.1 General Operating Modes22314.1.1 Synchronous and Trigger modes223FIGURE 14-1: Input Capture x Block Diagram22314.1.2 Cascaded (32-bit) Mode22414.2 Capture Operations224Register 14-1: ICxCON1: Input Capture x Control Register 1225Register 14-2: ICxCON2: Input Capture x Control Register 222615.0 Output Compare with Dedicated Timers22715.1 General Operating Modes22715.1.1 Synchronous and Trigger modes22715.1.2 Cascaded (32-bit) Mode227FIGURE 15-1: Output Compare x Block Diagram (16-bit Mode)22815.2 Compare Operations22815.3 Pulse-Width Modulation (PWM) Mode229FIGURE 15-2: Output Compare x Block Diagram (Double-Buffered, 16-bit PWM Mode)23015.3.1 PWM Period230EQUATION 15-1: Calculating the PWM Period(1)23015.3.2 PWM Duty Cycle231EQUATION 15-2: Calculation for Maximum PWM Resolution(1)231EXAMPLE 15-1: PWM Period and Duty Cycle Calculations(1)231TABLE 15-1: Example PWM Frequencies and Resolutions at 4 MIPS (Fcy = 4 MHz)(1)231TABLE 15-2: Example PWM Frequencies and Resolutions at 16 MIPS (Fcy = 16 MHz)(1)231Register 15-1: OCxCON1: Output Compare x Control Register 1232Register 15-2: OCxCON2: Output Compare x Control Register 223416.0 Serial Peripheral Interface (SPI)237FIGURE 16-1: SPIx Module Block Diagram (Standard Mode)238FIGURE 16-2: SPIx Module Block Diagram (Enhanced Mode)239Register 16-1: SPIxSTAT: SPIx Status and Control Register240Register 16-2: SPIxCON1: SPIx Control Register 1242Register 16-3: SPIxCON2: SPIx Control Register 2244FIGURE 16-3: SPIx Master/Slave Connection (Standard Mode)245FIGURE 16-4: SPIx Master/Slave Connection (Enhanced Buffer Modes)245FIGURE 16-5: SPIx Master, Frame Master Connection Diagram246FIGURE 16-6: SPIx Master, Frame Slave Connection Diagram246FIGURE 16-7: SPIx Slave, Frame Master Connection Diagram246FIGURE 16-8: SPIx Slave, Frame Slave Connection Diagram246EQUATION 16-1: Relationship Between Device and SPIx Clock Speed(1)247TABLE 16-1: Sample SCKx Frequencies(1,2)24717.0 Inter-Integrated Circuit™ (I2C™)24917.1 Communicating as a Master in a Single Master Environment249FIGURE 17-1: I2C™ Block Diagram25017.2 Setting Baud Rate When Operating as a Bus Master251EQUATION 17-1: Computing Baud Rate Reload Value(1,2)25117.3 Slave Address Masking251TABLE 17-1: I2C™ Clock Rates(1,2)251TABLE 17-2: I2C™ reserved addresses(1)251Register 17-1: I2CxCON: I2Cx Control Register252Register 17-2: I2CxSTAT: I2Cx Status Register254Register 17-3: I2CxMSK: I2Cx Slave Mode Address Mask Register25518.0 Universal Asynchronous Receiver Transmitter (UART)257FIGURE 18-1: UARTx Simplified Block Diagram25718.1 UARTx Baud Rate Generator (BRG)258EQUATION 18-1: UARTx Baud Rate with BRGH = 0(1,2)258EQUATION 18-2: UARTx Baud Rate with BRGH = 1(1,2)258EXAMPLE 18-1: Baud Rate Error Calculation (BRGH = 0)(1)25818.2 Transmitting in 8-Bit Data Mode25918.3 Transmitting in 9-Bit Data Mode25918.4 Break and Sync Transmit Sequence25918.5 Receiving in 8-Bit or 9-Bit Data Mode25918.6 Operation of UxCTS and UxRTS Control Pins25918.7 Infrared Support25918.7.1 IrDA Clock Output for External IrDA Support25918.7.2 Built-in IrDA Encoder and Decoder259Register 18-1: UxMODE: UARTx Mode Register260Register 18-2: UxSTA: UARTx Status and Control Register26219.0 Universal Serial Bus with On-The-Go Support (USB OTG)265TABLE 19-1: Controller-CENTRIC Data Direction for USB Host or Target265FIGURE 19-1: USB OTG Module Block Diagram26619.1 Hardware Configuration26719.1.1 Device Mode267FIGURE 19-2: Bus-Powered Interface Example267FIGURE 19-3: Self-power Only267FIGURE 19-4: Dual Power Example26719.1.2 Host and OTG Modes268FIGURE 19-5: Host Interface Example268FIGURE 19-6: OTG Interface Example26819.1.3 Using An External Interface26919.1.4 Calculating Transceiver Power Requirements269EQUATION 19-1: Estimating USB Transceiver Current Consumption26919.2 USB Buffer Descriptors and the BDT270FIGURE 19-7: BDT Mapping for Endpoint Buffering Modes27019.2.1 Buffer Ownership27119.2.2 DMA Interface271TABLE 19-2: Assignment of Buffer Descriptors for the Different Buffering Modes271Register 19-1: BDnSTAT: Buffer Descriptor n Status Register Prototype, USB Mode (BD0STAT through BD63STAT)272Register 19-2: BDnSTAT: Buffer Descriptor n Status Register Prototype, CPU Mode (BD0STAT Through BD63STAT)27319.3 USB Interrupts274FIGURE 19-8: USB OTG Interrupt Funnel27419.3.1 Clearing USB OTG Interrupts275FIGURE 19-9: Example of a USB Transaction and Interrupt Events27519.4 Device Mode Operation27519.4.1 Enabling device mode27519.4.2 Receiving an IN token in device mode27619.4.3 Receiving an OUT token in device mode27619.5 Host Mode Operation27619.5.1 Enable Host Mode and Discover a Connected Device27619.5.2 Complete a Control Transaction to a Connected Device27719.5.3 Send a Full-Speed Bulk Data Transfer to a Target Device27819.6 OTG Operation27819.6.1 Session Request Protocol (SRP)27819.6.2 Host Negotiation Protocol (HNP)27919.6.3 EXTERNAL Vbus COMPARATORS279TABLE 19-3: EXTERNAL Vbus COMPARATOR STATES27919.7 USB OTG Module Registers28019.7.1 USB OTG Module Control Registers281Register 19-3: U1OTGSTAT: USB OTG Status Register (Host Mode Only)281Register 19-4: U1OTGCON: USB On-the-Go Control Register282Register 19-5: U1PWRC: USB Power Control Register283Register 19-6: U1STAT: USB Status Register284Register 19-7: U1CON: USB Control Register (Device Mode)285Register 19-8: U1CON: USB Control Register (Host Mode Only)286Register 19-9: U1ADDR: USB Address Register287Register 19-10: U1TOK: USB Token Register (Host Mode Only)287Register 19-11: U1SOF: USB OTG Start-of-token Threshold Register (Host Mode Only)288Register 19-12: U1CNFG1: USB Configuration Register 1289Register 19-13: U1CNFG2: USB Configuration Register 229019.7.2 USB Interrupt Registers291Register 19-14: U1OTGIR: USB OTG Interrupt Status Register (Host mode Only)291Register 19-15: U1OTGIE: USB OTG Interrupt Enable Register (Host Mode Only)292Register 19-16: U1IR: USB Interrupt Status Register (Device Mode Only)293Register 19-17: U1IR: USB Interrupt Status Register (Host Mode Only)294Register 19-18: U1IE: USB Interrupt Enable Register (All USB Modes)295Register 19-19: U1EIR: USB Error Interrupt Status Register296Register 19-20: U1EIE: USB Error Interrupt Enable Register29719.7.3 USB Endpoint Management Registers298Register 19-21: U1EPn: USB Endpoint n Control Registers (n = 0 to 15)29820.0 Data Signal Modulator299FIGURE 20-1: Simplified Block Diagram of the Data Signal Modulator299Register 20-1: MDCON: Data Signal Modulator Control Register300Register 20-2: MDSRC: Data Signal Modulator Source Control Register301Register 20-3: MDCAR: Data Signal Modulator Carrier Control Register30221.0 Enhanced Parallel Master Port (EPMP)30321.1 Specific Package Variations303TABLE 21-1: EPMP Feature Differences By Device Pin Count303TABLE 21-2: Enhanced Parallel Master Port Pin Descriptions304Register 21-1: PMCON1: EPMP Control Register 1305Register 21-2: PMCON2: EPMP Control Register 2306Register 21-3: PMCON3: EPMP Control Register 3307Register 21-4: PMCON4: EPMP Control Register 4308Register 21-5: PMCSxCF: EPMP Chip Select x Configuration Register309Register 21-6: PMCSxBS: EPMP Chip Select x Base Address Register(2)310Register 21-7: PMCSxMD: EPMP Chip Select x Mode Register311Register 21-8: PMSTAT: EPMP Status Register (Slave mode only)312Register 21-9: PADCFG1: Pad Configuration Control Register31322.0 Liquid Crystal Display (LCD) Controller315FIGURE 22-1: LCD Controller Module Block Diagram31522.1 Registers316Register 22-1: LCDCON: LCD Control Register316Register 22-2: LCDREG: LCD Charge Pump Control Register317Register 22-3: LCDPS: LCD Phase Register318Register 22-4: LCDSEx: LCD SEGMENT x Enable Register319Register 22-5: LCDDATAx: LCD DATA x Register319TABLE 22-1: LCDDATA Registers And Bits For Segment And COM Combinations320Register 22-6: LCDREF: LCD Reference Ladder Control Register32123.0 Real-Time Clock and Calendar (RTCC)32323.1 RTCC Source Clock323FIGURE 23-1: RTCC Block Diagram32323.2 RTCC Module Registers32423.2.1 Register Mapping324TABLE 23-1: RTCVAL Register Mapping324TABLE 23-2: ALRMVAL Register Mapping32423.2.2 Write Lock32423.2.3 Selecting RTCC Clock Source324EXAMPLE 23-1: Setting the RTCWREN Bit32423.3 Registers32523.3.1 RTCC Control Registers325Register 23-1: RCFGCAL: RTCC Calibration/Configuration Register(1)325Register 23-2: RTCPWC: RTCC Power Control Register(1)327Register 23-3: ALCFGRPT: Alarm Configuration Register32823.3.2 RTCVAL Register Mappings329Register 23-4: YEAR: Year Value Register(1)329Register 23-5: MTHDY: Month and Day Value Register(1)329Register 23-6: WKDYHR: Weekday and Hours Value Register(1)330Register 23-7: MINSEC: Minutes and Seconds Value Register33023.3.3 ALRMVAL Register Mappings331Register 23-8: ALMTHDY: Alarm Month and Day Value Register(1)331Register 23-9: ALWDHR: Alarm Weekday and Hours Value Register(1)331Register 23-10: ALMINSEC: Alarm Minutes and Seconds Value Register33223.4 Calibration333EQUATION 23-1:33323.5 Alarm33323.5.1 Configuring The Alarm33323.5.2 Alarm Interrupt333FIGURE 23-2: Alarm Mask Settings33423.6 POWER CONTROL33423.7 RTCC Vbat OPERATION33424.0 32-Bit Programmable Cyclic Redundancy Check (CRC) Generator335FIGURE 24-1: CRC Block Diagram335FIGURE 24-2: CRC Shift Engine Detail33524.1 User Interface33624.1.1 Polynomial Interface336EQUATION 24-1: 16-Bit, 32-bit CRC Polynomials33624.1.2 DATA INTERFACE336TABLE 24-1: CRC SETUP EXAMPLES FOR 16 AND 32-BIT Polynomials33624.1.3 Data Shift Direction33724.1.4 Interrupt Operation33724.1.5 Typical Operation337Register 24-1: CRCCON1: CRC Control 1 Register338Register 24-2: CRCCON2: CRC Control 2 Register339Register 24-3: CRCXORL: CRC XOR POLYNOMIAL REGISTER, LOW BYTE339Register 24-4: CRCXORH: CRC XOR Polynomial Register, High Byte34025.0 Overview of Advanced Analog Features34125.1 Shared Analog Pins34125.2 Internal Band Gap References341FIGURE 25-1: Analog Block Overview342TABLE 25-1: Shared Analog Pins343Register 25-1: BUFCON0: Internal Voltage reference Control Register344Register 25-2: BUFCONx: Band Gap Buffers 1 and 2 Control Registers34526.0 12-Bit High-Speed, Pipeline A/D Converter34726.1 Basic Operation34726.2 Registers348FIGURE 26-1: 12-Bit Pipeline A/D Converter Block Diagram349Register 26-1: ADCON1: A/D Control Register 1350Register 26-2: ADCON2: A/D Control Register 2351Register 26-3: ADCON3: A/D Control Register 3352Register 26-4: ADSTATH: A/D Status High register353Register 26-5: ADSTATL: A/D Status Low register354Register 26-6: ADLnCONH: A/D Sample List n Control High Register (n = 0 to 3)355Register 26-7: ADLnCONL: A/D Sample List n Control Low Register (n = 0 to 3)357Register 26-8: ADlnSTAT: A/D Sample List n Status Register (n = 0 to 3)359Register 26-9: ADLnPTR: A/D Sample List n Pointer Register (n = 0 to 3)360Register 26-10: ADTBLn: A/D Sample Table Entry n Register (n = 0 to 31)360TABLE 26-1: Channel Entry Select Values for ADCH<6:0>361Register 26-11: ACCONh: A/D Accumulator Control High Register362Register 26-12: ACCONL: A/D Accumulator Control low Register362Register 26-13: ADCHITH: A/D Match Hit High Register363Register 26-14: ADCHITL: A/D Match Hit Low Register363Register 26-15: ADTHnH: A/D Sample Table n Threshold Value High Register (n = 0 to 3)364Register 26-16: ADTHnL: A/D Sample Table n Threshold Value Low Register (n = 0 to 3)364Register 26-17: ADLnMSEL3: A/D Sample List n Multi-channel select Register 3 (n = 0 to 3)365Register 26-18: ADLnMSEL2: A/D Sample List n Multi-channel select Register 2 (n = 0 to 3)365Register 26-19: ADLnMSEL1: A/D Sample List n Multi-channel select Register 1 (n = 0 to 3)366Register 26-20: ADLnMSEL0: A/D Sample List n Multi-channel select Register 0 (n = 0 to 3)366FIGURE 26-2: 12-Bit A/D Converter Single-Ended Analog Input Model367FIGURE 26-3: 12-bit A/D Transfer Function36827.0 16-Bit Sigma-Delta Analog-to-Digital (A/D) Converter369FIGURE 27-1: Sigma-Delta A/D Converter Block Diagram36927.1 Important Differences Compared to Conventional A/Ds37027.1.1 Result Quality and Oversampling37027.1.2 Uncorrected Offset Error37027.1.3 Uncorrected Gain Error370Register 27-1: SD1CON1: S/D Control Register 1371Register 27-2: SD1CON2: S/D Control Register 2372Register 27-3: SD1CON3: S/D Control Register 337328.0 10-Bit Digital-to-Analog Converter (DAC)375FIGURE 28-1: Single DAC Simplified Block Diagram375Register 28-1: DACxCON: DACx Control Register37629.0 Dual Operational Amplifier Module377FIGURE 29-1: Single operational Amplifier Block Diagram377Register 29-1: AMPxCON: OP AMP x Control Register37830.0 Triple Comparator Module381FIGURE 30-1: Triple Comparator Module Block Diagram381FIGURE 30-2: Individual Comparator Configurations when CREF = 0382FIGURE 30-3: Individual Comparator Configurations when CREF = 1 and CVREFP = 0383FIGURE 30-4: Individual Comparator Configurations when CREF = 1 and CVREFP = 1383Register 30-1: CMxCON: Comparator x Control Registers (Comparators 1 Through 3)384Register 30-2: CMSTAT: Comparator Module Status Register38531.0 Comparator Voltage Reference38731.1 Configuring the Comparator Voltage Reference387FIGURE 31-1: Comparator Voltage Reference Block Diagram387Register 31-1: CVRCON: Comparator Voltage Reference Control Register38832.0 Charge Time Measurement Unit (CTMU)38932.1 Measuring Capacitance389EQUATION 32-1:389FIGURE 32-1: Typical Connections and Internal Configuration for Capacitance Measurement39032.2 Measuring Time39032.3 Pulse Generation and Delay390FIGURE 32-2: Typical Connections and Internal Configuration for Time Measurement391FIGURE 32-3: Typical Connections and Internal Configuration for Pulse Delay Generation391Register 32-1: CTMUCON1: CTMU Control Register 1392Register 32-2: CTMUCON2: CTMU Control Register 2393Register 32-3: CTMUICON: CTMU current Control Register39533.0 High/Low-Voltage Detect (HLVD)397FIGURE 33-1: High/Low-Voltage Detect (HLVD) Module Block Diagram397Register 33-1: HLVDCON: High/Low-Voltage Detect Control Register39834.0 Special Features39934.1 Configuration Bits39934.1.1 Considerations for Configuring PIC24FJ128GC010 family Devices399TABLE 34-1: Flash Configuration Word Locations for PIC24FJ128GC010 family Devices399Register 34-1: CW1: Flash Configuration Word 1400Register 34-2: CW2: Flash Configuration Word 2402Register 34-3: CW3: Flash Configuration Word 3404Register 34-4: CW4: Flash Configuration Word 4406Register 34-5: DEVID: Device ID Register408Register 34-6: DEVREV: Device Revision Register40834.2 On-Chip Voltage Regulator409FIGURE 34-1: Connections for the On-Chip Regulator40934.2.1 On-Chip Regulator and POR40934.2.2 Voltage Regulator Standby Mode40934.2.3 Low-Voltage/Retention Regulator40934.3 Watchdog Timer (WDT)41034.3.1 Windowed Operation41034.3.2 Control Register410FIGURE 34-2: WDT Block Diagram41034.4 Program Verification and Code Protection41134.4.1 General Segment Protection41134.4.2 Code Segment Protection411TABLE 34-2: Code Segment Protection Configuration Options41134.4.3 Configuration Register Protection41234.5 JTAG Interface41234.6 In-Circuit Serial Programming41234.7 In-Circuit Debugger41235.0 Development Support41336.0 Instruction Set Summary417TABLE 36-1: Symbols Used in Opcode Descriptions418TABLE 36-2: Instruction Set Overview41937.0 Electrical Characteristics425Absolute Maximum Ratings(†)42537.1 DC Characteristics426FIGURE 37-1: PIC24FJ128GC010 family Voltage-Frequency Graph (Industrial)426TABLE 37-1: Thermal Operating Conditions426TABLE 37-2: Thermal Packaging Characteristics426TABLE 37-3: DC Characteristics: Temperature and Voltage Specifications427TABLE 37-4: DC Characteristics: Operating Current (Idd)428TABLE 37-5: DC Characteristics: Idle Current (Iidle)428TABLE 37-6: DC Characteristics: Power-Down Current (Ipd)429TABLE 37-7: DC Characteristics: D Current (BOR, WDT, DSBOR, DSWDT, LCD)430TABLE 37-8: DC Characteristics: I/O Pin Input Specifications431TABLE 37-9: DC Characteristics: I/O Pin Output Specifications432TABLE 37-10: DC Characteristics: Program Memory432TABLE 37-11: Internal Voltage Regulator Specifications433TABLE 37-12: Band gap Reference (BGBUFn) Specifications433TABLE 37-13: Vbat Operating Voltage Specifications434TABLE 37-14: CTMU Current Source Specifications434TABLE 37-15: USB On-The-Go Module Specifications434TABLE 37-16: High/Low-Voltage Detect Characteristics435TABLE 37-17: Comparator DC Specifications435TABLE 37-18: Comparator Voltage Reference DC Specifications435TABLE 37-19: Operational Amplifier Specifications43637.2 AC Characteristics and Timing Parameters437TABLE 37-20: Temperature and Voltage Specifications – AC437FIGURE 37-2: Load Conditions for Device Timing Specifications437TABLE 37-21: Capacitive Loading Requirements on Output Pins437FIGURE 37-3: External Clock Timing438TABLE 37-22: External Clock Timing Requirements438TABLE 37-23: PLL Clock Timing Specifications439TABLE 37-24: Internal RC Accuracy439TABLE 37-25: RC Oscillator Start-Up Time439FIGURE 37-4: CLKO and I/O Timing Characteristics440TABLE 37-26: CLKO and I/O Timing Requirements440TABLE 37-27: Reset and Brown-out Reset Requirements441TABLE 37-28: 12-Bit Pipeline A/D Module Specifications442FIGURE 37-5: 12-Bit A/D DNL, 10 MS/S, AVdd = 3.0V, Typical443FIGURE 37-6: 12-Bit A/D INL, 10 MS/S, AVdd = 3.0V, TYPICAL443TABLE 37-29: 12-Bit Pipeline A/D Conversion Timing Requirements(1)444TABLE 37-30: 10-Bit DAC Specifications444TABLE 37-31: 16-Bit Sigma-Delta A/D Converter Specifications445FIGURE 37-7: 16-Bit S/D A/D DNL, SVdd = 3.0V, TYPICAL446FIGURE 37-8: 16-Bit S/D A/D INL, SVdd = 3.0V, TYPICAL44638.0 Packaging Information44738.1 Package Marking Information44738.2 Package Marking Information (Continued)44838.3 Package Details449Appendix A: Revision History459Revision A (July 2012)459Revision B (May 2013)459INDEX461The Microchip Web Site467Customer Change Notification Service467Customer Support467Reader Response468Product Identification System469Worldwide Sales and Service472Dimensioni: 4,48 MBPagine: 472Language: EnglishApri il manuale
