Scheda TecnicaSommarioOperating Range:3High-Performance DSC CPU:3Direct Memory Access (DMA):3Interrupt Controller:3Digital I/O:3On-Chip Flash and SRAM:3System Management:3Power Management:3Timers/Capture/Compare/PWM:3Communication Modules:4Motor Control Peripherals:4Analog-to-Digital Converters (ADCs):4CMOS Flash Technology:4Packaging:4dsPIC33F Product Families5dsPIC33F General Purpose Family Variants5Pin Diagrams6Pin Diagrams (Continued)7Pin Diagrams (Continued)8Pin Diagrams (Continued)9Pin Diagrams (Continued)10Pin Diagrams (Continued)11Pin Diagrams (Continued)12Pin Diagrams (Continued)13dsPIC33F Motor Control Family Variants14Pin Diagrams15Pin Diagrams (Continued)16Pin Diagrams (Continued)17Pin Diagrams (Continued)18Pin Diagrams (Continued)19Pin Diagrams (Continued)20Pin Diagrams (Continued)21Table of Contents22Most Current Data Sheet23Errata23Customer Notification System231.0 Device Overview25FIGURE 1-1: dsPIC33F General Block Diagram26TABLE 1-1: Pinout I/O Descriptions272.0 CPU292.1 Data Addressing Overview292.2 DSP Engine Overview292.3 Special MCU Features29FIGURE 2-1: dsPIC33F CPU Core Block Diagram30FIGURE 2-2: dsPIC33F Programmer’s Model312.4 CPU Control Registers32Register 2-1: SR: CPU STATUS Register32Register 2-2: CORCON: CORE Control Register342.5 Arithmetic Logic Unit (ALU)352.5.1 Multiplier352.5.2 Divider352.6 DSP Engine35TABLE 2-1: DSP Instructions Summary35FIGURE 2-3: DSP Engine Block Diagram362.6.1 Multiplier372.6.2 Data Accumulators and Adder/Subtracter372.6.3 Barrel Shifter393.0 Memory Organization413.1 Program Address Space41FIGURE 3-1: Program Memory Map for dsPIC33F Family Devices413.1.1 Program Memory Organization423.1.2 Interrupt and Trap Vectors42FIGURE 3-2: Program Memory Organization423.2 Data Address Space433.2.1 Data Space Width433.2.2 Data Memory Organization and Alignment433.2.3 SFR Space433.2.4 Near Data Space43FIGURE 3-3: Data Memory Map for dsPIC33F Devices with 8 Kbs RAM44FIGURE 3-4: Data Memory Map for dsPIC33F Devices with 16 Kbs RAM45FIGURE 3-5: Data Memory Map for dsPIC33F Devices with 30 Kbs RAM463.2.5 X and Y Data Spaces473.2.6 DMA RAM47TABLE 3-1: CPU Core Registers Map48TABLE 3-2: Change Notification Register Map49TABLE 3-3: Interrupt Controller Register Map50TABLE 3-4: Timer Register Map51TABLE 3-5: Input Capture Register Map52TABLE 3-6: Output Compare Register Map53TABLE 3-7: 8-Output PWM Register Map54TABLE 3-8: QEI Register Map55TABLE 3-9: I2C1 Register Map55TABLE 3-10: I2C2 Register Map55TABLE 3-11: UART1 Register Map56TABLE 3-12: UART2 Register Map56TABLE 3-13: SPI1 Register Map56TABLE 3-14: SPI2 Register Map56TABLE 3-15: ADC1 Register Map57TABLE 3-16: ADC2 Register Map57TABLE 3-17: dma Register Map58TABLE 3-18: ECAN1 Register Map When C1CTRL1.WIN = 0 or 160TABLE 3-19: ECAN1 Register Map When C1CTRL1.WIN = 060TABLE 3-20: ECAN1 Register Map When C1CTRL1.WIN = 161TABLE 3-21: ECAN2 Register Map When C2CTRL1.WIN = 0 or 163TABLE 3-22: ECAN2 Register Map When C2CTRL1.WIN = 063TABLE 3-23: ECAN2 Register Map When C2CTRL1.WIN = 164TABLE 3-24: DCI Register Map66TABLE 3-25: PORTA Register Map(1)66TABLE 3-26: PORTB Register Map(1)66TABLE 3-27: PORTC Register Map(1)67TABLE 3-28: PORTD Register Map(1)67TABLE 3-29: PORTE Register Map(1)67TABLE 3-30: PORTF Register Map(1)67TABLE 3-31: PORTG Register Map(1)68TABLE 3-32: System Control Register Map68TABLE 3-33: NVM Register Map68TABLE 3-34: PMD Register Map683.2.7 Software Stack69FIGURE 3-6: CALL Stack Frame693.2.8 Data Ram Protection Feature693.3 Instruction Addressing Modes693.3.1 File Register Instructions693.3.2 MCU Instructions69TABLE 3-35: Fundamental Addressing Modes Supported703.3.3 Move and Accumulator Instructions703.3.4 MAC Instructions703.3.5 Other Instructions703.4 Modulo Addressing703.4.1 Start and End Address713.4.2 W Address Register Selection71FIGURE 3-7: Modulo Addressing Operation Example713.4.3 Modulo Addressing Applicability723.5 Bit-Reversed Addressing723.5.1 Bit-Reversed Addressing Implementation72FIGURE 3-8: Bit-Reversed Address Example73TABLE 3-36: Bit-Reversed Address Sequence (16-Entry)733.6 Interfacing Program and Data Memory Spaces743.6.1 Addressing Program Space74TABLE 3-37: Program Space Address Construction74FIGURE 3-9: Data Access from Program Space Address Generation753.6.2 Data Access From Program Memory Using Table Instructions76FIGURE 3-10: Accessing Program Memory with Table Instructions763.6.3 Reading Data From Program Memory Using Program Space Visibility77FIGURE 3-11: Program Space Visibility Operation774.0 Flash Program Memory794.1 Table Instructions and Flash Programming79FIGURE 4-1: Addressing for Table Registers794.2 RTSP Operation804.3 Control Registers804.4 Programming Operations80Register 4-1: NVMCON: Flash Memory Control Register814.4.1 Programming Algorithm for Flash Program Memory82EXAMPLE 4-1: Erasing a Program Memory Page82EXAMPLE 4-2: Loading the Write Buffers83EXAMPLE 4-3: Initiating a Programming Sequence835.0 Resets85FIGURE 5-1: Reset System Block Diagram85Register 5-1: RCON: Reset Control Register(1)86TABLE 5-1: Reset Flag Bit Operation875.1 Clock Source Selection at Reset87TABLE 5-2: Oscillator Selection vs. Type of Reset (Clock Switching Enabled)875.2 Device Reset Times87TABLE 5-3: Reset Delay Times for Various Device Resets885.2.1 POR and Long Oscillator Start-up Times885.2.2 Fail-Safe Clock Monitor (FSCM) and Device Resets885.3 Special Function Register Reset States886.0 Interrupt Controller896.1 Interrupt Vector Table896.1.1 Alternate Vector Table896.2 Reset Sequence89FIGURE 6-1: dsPIC33F Interrupt Vector Table90TABLE 6-1: Interrupt Vectors91TABLE 6-2: Trap Vectors926.3 Interrupt Control and Status Registers93Register 6-1: SR: CPU STATUS Register(1)94Register 6-2: CORCON: CORE Control Register(1)94Register 6-3: INTCON1: Interrupt Control Register 195Register 6-4: INTCON2: Interrupt Control Register 297Register 6-5: IFS0: Interrupt Flag Status Register 098Register 6-6: IFS1: Interrupt Flag Status Register 1100Register 6-7: IFS2: Interrupt Flag Status Register 2102Register 6-8: IFS3: Interrupt Flag Status Register 3104Register 6-9: IFS4: Interrupt Flag Status Register 4106Register 6-10: IEC0: Interrupt Enable Control Register 0107Register 6-11: IEC1: Interrupt Enable Control Register 1109Register 6-12: IEC2: Interrupt Enable Control Register 2111Register 6-13: IEC3: Interrupt Enable Control Register 3113Register 6-14: IEC4: Interrupt Enable Control Register 4115Register 6-15: IPC0: Interrupt Priority Control Register 0116Register 6-16: IPC1: Interrupt Priority Control Register 1117Register 6-17: IPC2: Interrupt Priority Control Register 2118Register 6-18: IPC3: Interrupt Priority Control Register 3119Register 6-19: IPC4: Interrupt Priority Control Register 4120Register 6-20: IPC5: Interrupt Priority Control Register 5121Register 6-21: IPC6: Interrupt Priority Control Register 6122Register 6-22: IPC7: Interrupt Priority Control Register 7123Register 6-23: IPC8: Interrupt Priority Control Register 8124Register 6-24: IPC9: Interrupt Priority Control Register 9125Register 6-25: IPC10: Interrupt Priority Control Register 10126Register 6-26: IPC11: Interrupt Priority Control Register 11127Register 6-27: IPC12: Interrupt Priority Control Register 12128Register 6-28: IPC13: Interrupt Priority Control Register 13129Register 6-29: IPC14: Interrupt Priority Control Register 14130Register 6-30: IPC15: Interrupt Priority Control Register 15131Register 6-31: IPC16: Interrupt Priority Control Register 16132Register 6-32: IPC17: Interrupt Priority Control Register 17133Register 6-33: INTTREG: Interrupt Control and Status Register1346.4 Interrupt Setup Procedures1356.4.1 Initialization1356.4.2 Interrupt Service Routine1356.4.3 Trap Service Routine1356.4.4 Interrupt Disable1357.0 Direct Memory Access (DMA)137TABLE 7-1: Peripherals with DMA Support137FIGURE 7-1: Top Level System Architecture Using a Dedicated Transaction Bus1387.1 DMAC Registers1387.2 DMAC Operating Modes1387.2.1 Byte or Word Transfer1397.2.2 Addressing Modes1397.2.3 DMA Transfer Direction1397.2.4 Null Data Peripheral Write Mode1397.2.5 Continuous or One-Shot Operation1407.2.6 ping-Pong Mode1407.2.7 Manual Transfer Mode1407.2.8 DMA Request Source Selection1407.3 DMA Interrupts and Traps1407.4 DMA Initialization Example141EXAMPLE 7-1: DMA Sample Initialization Method141Register 7-1: DMAxCON: DMA Channel x Control Register142Register 7-2: DMAxREQ: DMA Channel x IRQ Select Register143Register 7-3: DMAxSTA: DMA Channel x RAM Start Address Register A(1)144Register 7-4: DMAxSTB: DMA Channel x RAM Start Address Register B(1)144Register 7-5: DMAxPAD: DMA Channel x Peripheral Address Register(1)145Register 7-6: DMAxCNT: DMA Channel x Transfer Count Register(1)145Register 7-7: DMACS0: DMA Controller Status Register 0146Register 7-8: DMACS1: DMA Controller Status Register 1148Register 7-9: DSADR: Most Recent DMA RAM Address1498.0 Oscillator Configuration151FIGURE 8-1: dsPIC33F Oscillator System Diagram1518.1 CPU Clocking System1528.1.1 System Clock sources1528.1.2 System Clock Selection152EQUATION 8-1: Device Operating Frequency1528.1.3 PLL Configuration152EQUATION 8-2: Fosc Calculation152EQUATION 8-3: XT with PLL Mode Example153FIGURE 8-2: dsPIC33F PLL Block Diagram153TABLE 8-1: Configuration Bit Values for Clock Selection153Register 8-1: OSCCON: Oscillator Control Register154Register 8-2: CLKDIV: Clock Divisor Register155Register 8-3: PLLFBD: PLL Feedback Divisor Register156Register 8-4: OSCTUN: FRC Oscillator Tuning Register1578.2 Clock Switching Operation1588.2.1 Enabling Clock Switching1588.2.2 Oscillator Switching Sequence1588.3 Fail-Safe Clock Monitor (FSCM)1589.0 Power-Saving Features1599.1 Clock Frequency and Clock Switching1599.2 Instruction-Based Power-Saving Modes1599.2.1 Sleep Mode159EXAMPLE 9-1: PWRSAV Instruction Syntax1599.2.2 Idle Mode1609.2.3 Interrupts Coincident with Power Save Instructions1609.3 Doze Mode1609.4 Peripheral Module Disable16010.0 I/O Ports16110.1 Parallel I/O (PIO) Ports161FIGURE 10-1: Block Diagram of a Typical Shared Port Structure16110.2 Open-Drain Configuration16210.3 Configuring Analog Port Pins16210.4 I/O Port Write/Read Timing16210.5 Input Change Notification162EXAMPLE 10-1: Port Write/Read Example16211.0 Timer1163FIGURE 11-1: 16-bit Timer1 Module Block Diagram163Register 11-1: T1CON: Timer1 Control Register16412.0 Timer2/3, Timer4/5, Timer6/7 and Timer8/9165FIGURE 12-1: Timer2/3 (32-bit) Block Diagram(1)166FIGURE 12-2: Timer2 (16-bit) Block Diagram167Register 12-1: TxCON (T2CON, T4CON, T6CON or T8CON) Control Register168Register 12-2: TyCON (T3CON, T5CON, T7CON or T9CON) Control Register16913.0 Input Capture171FIGURE 13-1: Input Capture Block Diagram17113.1 Input Capture Registers172Register 13-1: ICxCON: Input Capture x Control Register17214.0 Output Compare17314.1 Setup for Single Output Pulse Generation17314.2 Setup for Continuous Output Pulse Generation17314.3 Pulse-Width Modulation Mode17414.3.1 PWM Period174EQUATION 14-1: Calculating the PWM Period17414.3.2 PWM Duty Cycle174EQUATION 14-2: Calculation for Maximum PWM Resolution174EXAMPLE 14-1: PWM Period and Duty Cycle Calculations174TABLE 14-1: Example PWM Frequencies and Resolutions at 4 MIPS (Fcy = 4 MHz)175TABLE 14-2: Example PWM Frequencies and Resolutions at 16 MIPS (Fcy = 16 MHz)175TABLE 14-3: Example PWM Frequencies and Resolutions at 40 MIPS (Fcy = 40 MHz)175FIGURE 14-1: Output Compare Module Block Diagram17514.4 Output Compare Register176Register 14-1: OCxCON: Output Compare x Control Register17615.0 Motor Control PWM Module177FIGURE 15-1: PWM Module Block Diagram17815.1 PWM Time Base17915.1.1 Free-Running Mode17915.1.2 Single-Shot Mode17915.1.3 Continuous Up/Down Count Modes17915.1.4 Double Update Mode18015.1.5 PWM Time Base Prescaler18015.1.6 PWM Time Base Postscaler18015.2 PWM Period180EQUATION 15-1: PWM Period180EQUATION 15-2: PWM Resolution18015.3 Edge-Aligned PWM180FIGURE 15-2: Edge-Aligned PWM18015.4 Center-Aligned PWM181FIGURE 15-3: Center-Aligned PWM18115.5 PWM Duty Cycle Comparison Units18115.5.1 Duty Cycle Register Buffers18115.5.2 Duty Cycle Immediate Updates18115.6 Complementary PWM Operation18215.7 Dead-Time Generators18215.7.1 Dead-Time Generators182FIGURE 15-4: Dead-Time Timing Diagram18215.7.2 Dead-Time Assignment183TABLE 15-1: Dead-Time Selection Bits18315.7.3 Dead-Time Ranges18315.8 Independent PWM Output18315.9 Single Pulse PWM Operation18315.10 PWM Output Override18315.10.1 Complementary Output Mode18315.10.2 Override Synchronization18415.11 PWM Output and Polarity Control18415.11.1 Output Pin Control18415.12 PWM Fault Pins18415.12.1 Fault Pin Enable Bits18415.12.2 Fault States18415.12.3 Fault Pin Priority18415.12.4 Fault Input Modes18515.13 PWM Update Lockout18515.14 PWM Special Event Trigger18515.14.1 Special Event Trigger Postscaler18515.15 PWM Operation During CPU Sleep Mode18515.16 PWM Operation During CPU Idle Mode185Register 15-1: PTCON: PWM Time Base Control Register186Register 15-2: PTMR: PWM Timer Count Value Register187Register 15-3: PTPER: PWM Time Base Period Register187Register 15-4: SEVTCMP: Special Event Compare Register188Register 15-5: PWMCON1: PWM Control Register 1189Register 15-6: PWMCON2: PWM Control Register 2190Register 15-7: DTCON1: Dead-Time Control Register 1191Register 15-8: DTCON2: Dead-Time Control Register 2192Register 15-9: FLTACON: Fault A Control Register193Register 15-10: FLTBCON: Fault B Control Register194Register 15-11: OVDCON: Override Control Register195Register 15-12: PDC1: PWM Duty Cycle Register 1196Register 15-13: PDC2: PWM Duty Cycle Register 2196Register 15-14: PDC3: PWM Duty Cycle Register 3197Register 15-15: PDC4: PWM Duty Cycle Register 419716.0 Quadrature Encoder Interface (QEI) Module199FIGURE 16-1: Quadrature Encoder Interface Block Diagram19916.1 Quadrature Encoder Interface Logic20016.2 16-bit Up/Down Position Counter Mode20016.2.1 Position Counter Error Checking20016.2.2 Position Counter Reset20016.2.3 Count Direction Status20016.3 Position Measurement Mode20016.4 Programmable Digital Noise Filters20116.5 Alternate 16-bit Timer/Counter20116.6 QEI Module Operation During CPU Sleep Mode20116.6.1 QEI Operation During CPU Sleep Mode20116.6.2 Timer Operation During CPU Sleep Mode20116.7 QEI Module Operation During CPU Idle Mode20116.7.1 QEI Operation During CPU Idle Mode20116.7.2 Timer Operation During CPU Idle Mode20216.8 Quadrature Encoder Interface Interrupts20216.9 Control and Status Registers202Register 16-1: QEICON: QEI Control Register 203Register 16-2: DFLTCON: Digital Filter Control Register 20517.0 Serial Peripheral Interface (SPI)207FIGURE 17-1: SPI Module Block Diagram208FIGURE 17-2: SPI Master/Slave Connection209FIGURE 17-3: SPI Master, Frame Master Connection Diagram209FIGURE 17-4: SPI Master, Frame Slave Connection Diagram209FIGURE 17-5: SPI Slave, Frame Master Connection Diagram210FIGURE 17-6: SPI Slave, Frame Slave Connection Diagram210EQUATION 17-1: Relationship Between Device and SPI Clock Speed210TABLE 17-1: Sample SCKx Frequencies210Register 17-1: SPIxSTAT: SPIx Status and Control Register211Register 17-2: SPIxCON1: SPIx Control Register 1212Register 17-3: SPIxCON2: SPIx Control Register 221318.0 Inter-Integrated Circuit (I2C)21518.1 Operating Modes21518.2 I2C Registers21518.3 I2C Interrupts21518.4 Baud Rate Generator215FIGURE 18-1: I2C™ Block Diagram (x = 1 or 2)21618.5 I2C Module Addresses217TABLE 18-1: 7-bit I2C™ Slave Addresses supported by dsPIC33F21718.6 Slave Address Masking21718.7 IPMI Support21718.8 General Call Address Support21718.9 Automatic Clock Stretch21718.9.1 Transmit Clock Stretching21718.9.2 Receive Clock Stretching21718.10 Software Controlled Clock Stretching (STREN = 1)21718.11 Slope Control21818.12 Clock Arbitration21818.13 Multi-Master Communication, Bus Collision and Bus Arbitration218Register 18-1: I2CxCON: I2Cx Control Register219Register 18-2: I2CxSTAT: I2Cx Status Register221Register 18-3: I2CxMSK: I2Cx Slave Mode Address Mask Register22319.0 Universal Asynchronous Receiver Transmitter (UART)225FIGURE 19-1: UART Simplified Block Diagram22519.1 UART Baud Rate Generator (BRG)226EQUATION 19-1: UART Baud Rate With BRGH = 0226EQUATION 19-2: UART Baud Rate With BRGH = 1226EXAMPLE 19-1: Baud Rate Error Calculation (BRGH = 0)22619.2 Transmitting in 8-bit Data Mode22719.3 Transmitting in 9-bit Data Mode22719.4 Break and Sync Transmit Sequence22719.5 Receiving in 8-bit or 9-bit Data Mode22719.6 Flow Control Using UxCTS and UxRTS Pins22719.7 Infrared Support22719.7.1 External IrDA Support – IrDA Clock Output22719.7.2 Built-in IrDA Encoder and Decoder227Register 19-1: UxMODE: UARTx Mode Register228Register 19-2: UxSTA: UARTx Status and Control Register23020.0 Enhanced CAN Module23320.1 Overview23320.2 Frame Types233FIGURE 20-1: ECAN™ Module Block Diagram23420.3 Modes of Operation23520.3.1 Initialization Mode23520.3.2 Disable Mode23520.3.3 Normal Operation Mode23520.3.4 Listen Only Mode23520.3.5 Listen All Messages Mode23520.3.6 Loopback Mode23520.4 Message Reception23520.4.1 Receive Buffers23520.4.2 FIFO Buffer Mode23620.4.3 Message Acceptance Filters23620.4.4 Message Acceptance Filter Masks23620.4.5 Receive Errors23620.4.6 Receive Interrupts23620.5 Message Transmission23720.5.1 Transmit Buffers23720.5.2 Transmit Message Priority23720.5.3 Transmission Sequence23720.5.4 Automatic Processing of Remote Transmission Requests23720.5.5 Aborting Message Transmission23720.5.6 Transmission Errors23720.5.7 Transmit Interrupts23820.6 Baud Rate Setting23820.6.1 Bit Timing238FIGURE 20-2: ECAN™ Module Bit Timing23820.6.2 Prescaler Setting239EQUATION 20-1: Time Quantum for Clock Generation23920.6.3 Propagation Segment23920.6.4 Phase Segments23920.6.5 Sample Point23920.6.6 Synchronization239Register 20-1: CiCTRL1: eCAN Control Register 1240Register 20-2: CiCTRL2: eCAN Control Register 2241Register 20-3: CiVEC: eCAN Interrupt Code Register242Register 20-4: CiFCTRL: eCAN FIFO Control Register243Register 20-5: CiFIFO: eCAN FIFO Status Register244Register 20-6: CiINTF: eCAN Interrupt Flag Register245Register 20-7: CiINTE: eCAN Interrupt Enable Register246Register 20-8: CiEC: eCAN Transmit/Receive Error Count Register247Register 20-9: CiCFG1: eCAN Baud Rate Configuration Register 1248Register 20-10: CiCFG2: eCAN Baud Rate Configuration Register 2249Register 20-11: CiFEN1: ECAN Acceptance Filter Enable Register250Register 20-12: CiBUFPNT1: ECAN Filter 0-3 Buffer Pointer Register250Register 20-13: CiBUFPNT2: ECAN Filter 4-7 Buffer Pointer Register251Register 20-14: CiBUFPNT3: ECAN Filter 8-11 Buffer Pointer Register251Register 20-15: CiBUFPNT4: ECAN Filter 12-15 Buffer Pointer Register252Register 20-16: CiRXFnSID: ECAN Acceptance Filter n Standard Identifier (n = 0, 1, ..., 15)253Register 20-17: CiRXFnEID: ECAN Acceptance Filter n Extended Identifier (n = 0, 1, ..., 15)253Register 20-18: CiFMSKSEL1: ECAN Filter 7-0 Mask Selection Register254Register 20-19: CiRXMnSID: ECAN Acceptance Filter Mask n Standard Identifier255Register 20-20: CiRXMnEID: ECAN Acceptance Filter Mask n Extended Identifier255Register 20-21: CiRXFUL1: ECAN Receive Buffer Full Register 1256Register 20-22: CiRXFUL2: ECAN Receive Buffer Full Register 2256Register 20-23: CiRXOVF1: ECAN Receive Buffer Overflow Register 1257Register 20-24: CiRXOVF2: ECAN Receive Buffer Overflow Register 2257Register 20-25: CiTRmnCON: ECAN TX/RX Buffer m Control Register (m = 0,2,4,6; n = 1,3,5,7)258Register 20-26: CiTRBnSID: ECAN Buffer n Standard Identifier (n = 0, 1, ..., 31)259Register 20-27: CiTRBnEID: ECAN Buffer n Extended Identifier (n = 0, 1, ..., 31)259Register 20-28: CiTRBnDLC: ECAN Buffer n Data Length Control (n = 0, 1, ..., 31)260Register 20-29: CiTRBnDm: ECAN Buffer n Data Field Byte m (n = 0, 1, ..., 31; m = 0, 1, ..., 7)(1)260Register 20-30: CiTRBnSTAT: ECAN Receive Buffer n Status (n = 0, 1, ..., 31)26121.0 Data Converter Interface (DCI) Module26321.1 Module Introduction26321.2 Module I/O Pins26321.2.1 CSCK Pin26321.2.2 CSDO Pin26321.2.3 CSDI Pin26321.2.4 Buffer Data Alignment26321.2.5 Transmit/Receive Shift Register26321.2.6 DCI Buffer Control263FIGURE 21-1: DCI Module Block Diagram26421.3 DCI Module Operation26521.3.1 Module Enable26521.3.2 Word Size Selection Bits26521.3.3 Frame Sync Generator265EQUATION 21-1: COFSG Period26521.3.4 Frame Sync Mode Control Bits26521.3.5 Master Frame Sync Operation26521.3.6 Slave Frame Sync Operation266FIGURE 21-2: Frame Sync Timing, Multi-Channel Mode266FIGURE 21-3: Frame Sync Timing, AC-Link Start-Of-Frame266FIGURE 21-4: I2S Interface Frame Sync Timing26621.3.7 Bit Clock Generator267EQUATION 21-2: Bit Clock Frequency267TABLE 21-1: Device Frequencies for Common Codec CSCK Frequencies26721.3.8 Sample Clock Edge Control Bit26821.3.9 Data Justification Control Bit26821.3.10 Transmit Slot Enable Bits26821.3.11 Receive Slot Enable Bits26821.3.12 Slot Enable Bits Operation with Frame SynC26821.3.13 Synchronous Data Transfers26821.3.14 Buffer Length Control26921.3.15 Buffer Alignment With Data Frames26921.3.16 Transmit STATUS BITS26921.3.17 RECEIVE STATUS bits26921.3.18 SLOT Status Bits27021.3.19 CSDO Mode Bit27021.3.20 Digital Loopback mode27021.3.21 Underflow Mode Control Bit27021.4 DCI Module Interrupts27021.5 DCI Module Operation During CPU Sleep and Idle Modes27021.5.1 DCI Module Operation During CPU Sleep Mode27021.5.2 DCI Module Operation During CPU Idle Mode27021.6 AC-Link Mode Operation27021.6.1 16-bit AC-link Mode27021.6.2 20-bit AC-Link Mode27121.7 I2S Mode Operation27121.7.1 I2S Frame and data word Length Selection27121.7.2 I2S DATA Justification271Register 21-1: DCICON1: DCI Control Register 1272Register 21-2: DCICON2: DCI Control Register 2273Register 21-3: DCICON3: DCI Control Register 3274Register 21-4: DCISTAT: DCI Status Register275Register 21-5: RSCON: DCI Receive Slot Control Register276Register 21-6: TSCON: DCI Transmit Slot Control Register27622.0 10-bit/12-bit Analog-to-Digital Converter (ADC)27722.1 Key Features27722.2 ADC Initialization27722.3 ADC and DMA277FIGURE 22-1: ADC1 Module Block Diagram278FIGURE 22-2: ADC2 Module Block Diagram(1)279EQUATION 22-1: ADC Conversion Clock Period280FIGURE 22-3: ADC Transfer Function (10-bit Example)280FIGURE 22-4: ADC Conversion Clock Period Block Diagram280Register 22-1: ADxCON1: ADCx control register 1(where x = 1 or 2)281Register 22-2: ADxCON2: ADCx control register 2 (where x = 1 or 2)283Register 22-3: ADxCON3: ADCx Control Register 3285Register 22-4: ADxCON4: ADCx Control Register 4286Register 22-5: ADxCHS123: ADCx INPUT Channel 1, 2, 3 select Register287Register 22-6: ADxCHS0: ADCx INPUT Channel 0 select Register288Register 22-7: ADxCSSH: ADCx INPUT SCAN SELECT register High(1)289Register 22-8: ADxCSSL: ADCx INPUT SCAN SELECT register Low(1)289Register 22-9: AD1PCFGH: ADC1 Port configuration register hIGH(1,2)290Register 22-10: ADxPCFGL: ADCx Port configuration register Low(1,2)29023.0 Special Features29123.1 Configuration Bits291TABLE 23-1: Device Configuration Register Map291TABLE 23-2: dsPIC33F Configuration Bits Description29223.2 On-Chip Voltage Regulator295FIGURE 23-1: Connections for the On-Chip Voltage Regulator(1)29523.3 Watchdog Timer (WDT)296FIGURE 23-2: WDT Block Diagram29623.4 JTAG Interface29723.5 Code Protection and CodeGuard™ Security29723.6 In-Circuit Serial Programming29723.7 In-Circuit Debugger29724.0 Instruction Set Summary299TABLE 24-1: Symbols used in Opcode Descriptions300TABLE 24-2: Instruction Set OVERVIEW30225.0 Development Support30725.1 MPLAB Integrated Development Environment Software30725.2 MPASM Assembler30825.3 MPLAB C18 and MPLAB C30 C Compilers30825.4 MPLINK Object Linker/ MPLIB Object Librarian30825.5 MPLAB ASM30 Assembler, Linker and Librarian30825.6 MPLAB SIM Software Simulator30825.7 MPLAB ICE 2000 High-Performance In-Circuit Emulator30925.8 MPLAB ICE 4000 High-Performance In-Circuit Emulator30925.9 MPLAB ICD 2 In-Circuit Debugger30925.10 MPLAB PM3 Device Programmer30925.11 PICSTART Plus Development Programmer31025.12 PICkit 2 Development Programmer31025.13 Demonstration, Development and Evaluation Boards31026.0 Electrical Characteristics311Absolute Maximum Ratings(Note 1)31126.1 DC Characteristics312TABLE 26-1: Operating MIPS vs. Voltage312TABLE 26-2: Thermal Operating Conditions312TABLE 26-3: Thermal Packaging Characteristics312TABLE 26-4: DC Temperature and Voltage specifications312TABLE 26-5: DC Characteristics: Operating Current (Idd) 313TABLE 26-6: DC Characteristics: Idle Current (iidle)314TABLE 26-7: DC Characteristics: Power-Down Current (Ipd)314TABLE 26-8: DC Characteristics: doze Current (Idoze)315TABLE 26-9: DC Characteristics: I/O Pin Input Specifications316TABLE 26-10: DC Characteristics: I/O Pin Output Specifications317TABLE 26-11: DC Characteristics: Program Memory317TABLE 26-12: Internal Voltage Regulator Specifications31726.2 AC Characteristics and Timing Parameters318TABLE 26-13: Temperature and Voltage Specifications – AC318FIGURE 26-1: Load Conditions for Device Timing Specifications318TABLE 26-14: cAPAcITIVE lOADING rEQUIREMENTS ON oUTPUT pINS318FIGURE 26-2: External Clock Timing319TABLE 26-15: External Clock Timing Requirements319TABLE 26-16: PLL Clock Timing Specifications (Vdd = 3.0V to 3.6V)320TABLE 26-17: AC Characteristics: Internal RC Accuracy320TABLE 26-18: Internal RC accuracy320FIGURE 26-3: CLKO and I/O Timing Characteristics321TABLE 26-19: CLKO and I/O Timing Requirements321FIGURE 26-4: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing Character...322TABLE 26-20: Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and Brown-out Reset...323FIGURE 26-5: Timer1, 2, 3, 4, 5, 6, 7, 8 and 9 External Clock Timing Characteristics324TABLE 26-21: Timer1 External Clock Timing Requirements(1)324TABLE 26-22: Timer2, Timer4, Timer6 and Timer8 External Clock Timing Requirements325TABLE 26-23: Timer3, Timer5, Timer7 and Timer9 External Clock Timing Requirements325FIGURE 26-6: TimerQ (QEI Module) External Clock Timing Characteristics326TABLE 26-24: QEI module External Clock Timing Requirements326FIGURE 26-7: INPUT CAPTURE (CAPx) TIMING Characteristics327TABLE 26-25: Input Capture timing requirements327FIGURE 26-8: Output Compare Module (OCx) Timing Characteristics327TABLE 26-26: Output Compare Module timing requirements327FIGURE 26-9: OC/PWM Module Timing Characteristics328TABLE 26-27: Simple OC/PWM MODE Timing Requirements328FIGURE 26-10: Motor Control PWM Module fault Timing Characteristics329FIGURE 26-11: Motor Control PWM Module Timing Characteristics329TABLE 26-28: Motor Control PWM Module Timing Requirements329FIGURE 26-12: QEA/QEB Input Characteristics330TABLE 26-29: Quadrature Decoder Timing Requirements330FIGURE 26-13: QEI Module Index Pulse Timing Characteristics331TABLE 26-30: QEI INDEX PULSE Timing Requirements331FIGURE 26-14: SPIx Module Master Mode (CKE = 0) Timing Characteristics332TABLE 26-31: SPIx Master mode (cke = 0) Timing requirements332FIGURE 26-15: SPIx Module Master Mode (CKE = 1) Timing Characteristics333TABLE 26-32: SPIx Module Master mode (cke = 1) Timing requirements333FIGURE 26-16: SPIx Module Slave Mode (CKE = 0) Timing Characteristics334TABLE 26-33: SPIx Module Slave mode (cke = 0) Timing requirements334FIGURE 26-17: SPIx Module Slave Mode (CKE = 1) Timing Characteristics335TABLE 26-34: SPIx Module Slave mode (cke = 1) Timing requirements 336FIGURE 26-18: I2Cx Bus Start/Stop Bits Timing Characteristics (Master Mode)337FIGURE 26-19: I2Cx Bus Data Timing Characteristics (Master mode)337TABLE 26-35: I2Cx Bus Data Timing Requirements (Master Mode)338FIGURE 26-20: I2Cx Bus Start/Stop Bits Timing Characteristics (slave mode)339FIGURE 26-21: I2Cx Bus Data Timing Characteristics (slave mode)339TABLE 26-36: I2Cx Bus Data Timing Requirements (Slave Mode)340FIGURE 26-22: DCI Module (Multi-channel, I2S modes) Timing Characteristics341TABLE 26-37: DCI Module (Multi-channel, I2S modes) Timing Requirements342FIGURE 26-23: DCI Module (AC-link mode) Timing Characteristics343TABLE 26-38: DCI Module (AC-Link Mode) Timing Requirements344FIGURE 26-24: CAN Module I/O Timing Characteristics345TABLE 26-39: CAN Module I/O Timing Requirements345TABLE 26-40: ADC Module Specifications345FIGURE 26-25: ADC Conversion (10-bit mode) Timing Characteristics (chps<1:0> = 01, SIMSAM = 0, as...348FIGURE 26-26: ADC Conversion (10-bit mode) Timing cHARACTERISTICS (chps<1:0> = 01, SIMSAM = 0, as...349TABLE 26-41: ADC CONVERSION (10-bit mode) TIMING rEQUIREMENTS350FIGURE 26-27: ADC Conversion (12-bit mode) Timing Characteristics (asam = 0, ssrc<2:0> = 000)351TABLE 26-42: ADC Conversion (12-bit Mode) TiminG rEQUIREMENTS)35227.0 Packaging Information35327.1 Package Marking Information35327.2 Package Details354Appendix A: Revision History359The Microchip Web Site367Customer Change Notification Service367Customer Support367Reader Response368Product Identification System369Worldwide Sales and Service370Dimensioni: 5 MBPagine: 370Language: EnglishApri il manuale