Scheda TecnicaSommarioOperating Conditions1Clock Management1Core Performance1Motor Control PWM1Advanced Analog Features1Input/Output1System Peripherals1Communication Interfaces1Direct Memory Access (DMA)1Qualification and Class B Support1Debugger Development Support1Packages1dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 and dsPIC33FJ128MCX02/X04 Product Families2Pin Diagrams3Pin Diagrams (Continued)4Pin Diagrams (Continued)5Pin Diagrams (Continued)6Pin Diagrams (Continued)7Table of Contents8Most Current Data Sheet9Errata9Customer Notification System9Referenced Sources101.0 Device Overview11FIGURE 1-1: dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 and dsPIC33FJ128MCX02/ X04 Block Diagram12TABLE 1-1: Pinout I/O Descriptions (Continued)132.0 Guidelines for Getting Started with 16-bit Digital Signal Controllers172.1 Basic Connection Requirements172.2 Decoupling Capacitors17FIGURE 2-1: Recommended Minimum connection182.2.1 Tank Capacitors182.3 CPU Logic Filter Capacitor Connection (Vcap)182.4 Master Clear (MCLR) Pin18FIGURE 2-2: Example of MCLR Pin Connections182.5 ICSP Pins192.6 External Oscillator Pins19FIGURE 2-3: Suggested Placement of the Oscillator Circuit19TABLE 2-1: Crystal Recommendations19TABLE 2-2: Resonator Recommendations202.7 Oscillator Value Conditions on Device Start-up202.8 Configuration of Analog and Digital Pins During ICSP Operations202.9 Unused I/Os203.0 CPU213.1 Overview213.2 Data Addressing Overview213.3 DSP Engine Overview223.4 Special MCU Features22FIGURE 3-1: dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 and dsPIC33FJ128MCX02/ X04 CPU Core Block Diagram23FIGURE 3-2: dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 and dsPIC33FJ128MCX02/ X04 Programmer’s Model243.5 CPU Resources253.5.1 Key Resources253.6 CPU Control Registers26Register 3-1: SR: CPU STATUS Register (Continued)26Register 3-2: CORCON: CORE Control Register (Continued)283.7 Arithmetic Logic Unit (ALU)303.7.1 Multiplier303.7.2 Divider303.8 DSP Engine30TABLE 3-1: DSP Instructions Summary30FIGURE 3-3: DSP Engine Block Diagram313.8.1 Multiplier323.8.2 Data Accumulators and Adder/Subtracter323.8.3 Accumulator Write Back333.8.4 Barrel Shifter344.0 Memory Organization354.1 Program Address Space35FIGURE 4-1: Program Memory Map for dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/ X04 and dsPIC33FJ128MCX02/X04 Devices354.1.1 Program Memory Organization364.1.2 Interrupt and Trap Vectors36FIGURE 4-2: Program Memory Organization364.2 Data Address Space374.2.1 Data Space Width374.2.2 Data Memory Organization and Alignment374.2.3 SFR Space374.2.4 Near Data Space37FIGURE 4-3: Data Memory Map for dsPIC33FJ32MC302/304 Devices with 4 Kb RAM38FIGURE 4-4: Data Memory Map for dsPIC33FJ128MC202/204 and dsPIC33FJ64MC202/ 204 Devices with 8 Kb RAM39FIGURE 4-5: Data Memory Map for dsPIC33FJ128MC802/804 And dsPIC33FJ64MC802/ 804 Devices with 16 Kb RAM404.2.5 X and Y Data Spaces414.2.6 DMA RAM414.3 Memory Resources414.3.1 Key Resources414.4 Special Function Register Maps42TABLE 4-1: CPU Core Registers Map (Continued)42TABLE 4-2: Change Notification Register Map for dsPIC33FJ128MC202/802, dsPIC33FJ64MC202/802 and dsPIC33FJ32MC30244TABLE 4-3: Change Notification Register Map for dsPIC33FJ128MC204/804, dsPIC33FJ64MC204/804 and dsPIC33FJ32MC30444TABLE 4-4: Interrupt Controller Register Map45TABLE 4-5: Timer Register Map46TABLE 4-6: Input Capture Register Map46TABLE 4-7: Output Compare Register Map47TABLE 4-8: 6-Output PWM1 Register Map47TABLE 4-9: 2-Output PWM2 Register Map48TABLE 4-10: QEI1 Register Map48TABLE 4-11: QEI2 Register Map48TABLE 4-12: I2C1 Register Map49TABLE 4-13: UART1 Register Map49TABLE 4-14: UART2 Register Map49TABLE 4-15: SPI1 Register Map50TABLE 4-16: SPI2 Register Map50TABLE 4-17: ADC1 Register Map For dsPIC33FJ64MC202/802, dsPIC33FJ128MC202/802 AND dsPIC33FJ32MC30250TABLE 4-18: ADC1 Register Map FOR dsPIC33FJ64MC204/804, dsPIC33FJ128MC204/804 AND dsPIC33FJ32MC30451TABLE 4-19: DAC1 Register Map For dsPIC33FJ128MC804 and dsPIC33FJ64MC80451TABLE 4-20: dma Register Map (Continued)52TABLE 4-21: ECAN1 Register Map When C1CTRL1.WIN = 0 or 1 (For dsPIC33FJ128MC802/804 and dsPIC33FJ64MC802/804)54TABLE 4-22: ECAN1 Register Map When C1CTRL1.WIN = 0 (For dsPIC33FJ128MC802/804 and dsPIC33FJ64MC802/804)54TABLE 4-23: ECAN1 Register Map When C1CTRL1.WIN = 1 (For dsPIC33FJ128MC802/804 and dsPIC33FJ64MC802/804) (Continued)55TABLE 4-24: PERIPHERAL pin select INPUT Register Map57TABLE 4-25: PERIPHERAL pin select outPUT Register Map FOR dsPIC33FJ128MC202/802, dsPIC33FJ64MC202/802 AND dsPIC33FJ32MC30258TABLE 4-26: PERIPHERAL pin select outPUT Register Map For dsPIC33FJ128MC204/804, dsPIC33FJ64MC204/804 AND dsPIC33FJ32MC30458TABLE 4-27: Parallel Master/Slave Port Register Map For dsPIC33FJ128MC202/802, dsPIC33FJ64MC202/802 AND dsPIC33FJ32MC30259TABLE 4-28: Parallel Master/Slave Port Register Map For dsPIC33FJ128MC204/804, dsPIC33FJ64MC204/804 AND dsPIC33FJ32MC30459TABLE 4-29: Real-Time Clock and Calendar Register Map60TABLE 4-30: CRC Register Map60TABLE 4-31: Dual Comparator Register Map60TABLE 4-32: PORTA Register Map For dsPIC33FJ128MC202/802, dsPIC33FJ64MC202/802 AND dsPIC33FJ32MC30260TABLE 4-33: PORTA Register Map For dsPIC33FJ128MC204/804, dsPIC33FJ64MC204/804 AND dsPIC33FJ32MC30461TABLE 4-34: PORTB Register Map61TABLE 4-35: PORTC Register Map For dsPIC33FJ128MC204/804, dsPIC33FJ64MC204/804 And dsPIC33FJ32MC30461TABLE 4-36: System Control Register Map61TABLE 4-37: sECURITY Register Map for dsPIC33FJ128MC204/804 and dsPIC33FJ64MC204/804 Only62TABLE 4-38: NVM Register Map62TABLE 4-39: pmd Register Map624.4.1 Software Stack63FIGURE 4-6: CALL Stack Frame634.4.2 Data Ram Protection Feature634.5 Instruction Addressing Modes634.5.1 File Register Instructions634.5.2 MCU Instructions63TABLE 4-40: Fundamental Addressing Modes Supported644.5.3 Move and Accumulator Instructions644.5.4 MAC Instructions644.5.5 Other Instructions644.6 Modulo Addressing654.6.1 Start and End Address654.6.2 W Address Register Selection65FIGURE 4-7: Modulo Addressing Operation Example654.6.3 Modulo Addressing Applicability664.7 Bit-Reversed Addressing664.7.1 Bit-Reversed Addressing Implementation66FIGURE 4-8: Bit-Reversed Address Example67TABLE 4-41: Bit-Reversed Address Sequence (16-Entry)674.8 Interfacing Program and Data Memory Spaces684.8.1 Addressing Program Space68TABLE 4-42: Program Space Address Construction68FIGURE 4-9: Data Access from Program Space Address Generation694.8.2 Data Access From Program Memory Using Table Instructions70FIGURE 4-10: Accessing Program Memory with Table Instructions704.8.3 Reading Data from Program Memory Using Program Space Visibility71FIGURE 4-11: Program Space Visibility Operation715.0 Flash Program Memory735.1 Table Instructions and Flash Programming73FIGURE 5-1: Addressing for Table Registers735.2 RTSP Operation745.3 Programming Operations74EQUATION 5-1: Programming Time74EQUATION 5-2: Minimum Row Write Time74EQUATION 5-3: Maximum Row Write Time745.4 Control Registers745.5 Flash Programming Resources745.5.1 Key Resources745.6 Flash Memory Control Registers75Register 5-1: NVMCON: Flash Memory Control Register75Register 5-2: NVMKEY: NonVolatile Memory Key RegisteR765.6.1 Programming Algorithm for Flash Program Memory77EXAMPLE 5-1: Erasing a Program Memory Page77EXAMPLE 5-2: Loading the Write Buffers78EXAMPLE 5-3: Initiating a Programming Sequence786.0 Resets79FIGURE 6-1: Reset System Block Diagram796.1 Resets Resources806.1.1 Key Resources806.2 Reset Control Registers81Register 6-1: RCON: Reset Control Register(1) (Continued)816.3 System Reset83TABLE 6-1: Oscillator Delay83FIGURE 6-2: System Reset Timing84TABLE 6-2: Oscillator Parameters856.4 Power-on Reset (POR)856.4.1 Brown-out Reset (BOR) and Power-up Timer (PWRT)85FIGURE 6-3: Brown-out Situations866.5 External Reset (EXTR)866.5.0.1 External supervisory circuit866.5.0.2 Internal Supervisory Circuit866.6 Software RESET Instruction (SWR)866.7 Watchdog Time-out Reset (WDTO)866.8 Trap Conflict Reset866.9 Configuration Mismatch Reset876.10 Illegal Condition Device Reset876.10.0.1 Illegal Opcode Reset876.10.0.2 Uninitialized W Register Reset876.10.0.3 Security Reset876.11 Using the RCON Status Bits87TABLE 6-3: Reset Flag Bit Operation(1)877.0 Interrupt Controller897.1 Interrupt Vector Table897.1.1 Alternate Interrupt Vector Table897.2 Reset Sequence89FIGURE 7-1: dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 and dsPIC33FJ128MCX02/ X04 Interrupt Vector Table90TABLE 7-1: Interrupt Vectors (Continued)917.3 Interrupt Control and Status Registers937.3.1 INTCON1 and INTCON2937.3.2 IFSx937.3.3 IECx937.3.4 IPCx937.3.5 INTTREG937.3.6 status/Control registers937.4 Interrupts Resources937.4.1 Key Resources937.5 Interrupt Registers94Register 7-1: SR: CPU STATUS Register(1)94Register 7-2: CORCON: CORE Control Register(1)94Register 7-3: INTCON1: Interrupt Control Register 1 (Continued)95Register 7-4: INTCON2: Interrupt Control Register 297Register 7-5: IFS0: Interrupt Flag Status Register 0 (Continued)98Register 7-6: IFS1: Interrupt Flag Status Register 1 (Continued)100Register 7-7: IFS2: Interrupt Flag Status Register 2102Register 7-8: IFS3: Interrupt Flag Status Register 3103Register 7-9: IFS4: Interrupt Flag Status Register 4104Register 7-10: IEC0: Interrupt Enable Control Register 0 (Continued)105Register 7-11: IEC1: Interrupt Enable Control Register 1 (Continued)107Register 7-12: IEC2: Interrupt Enable Control Register 2109Register 7-13: IEC3: Interrupt Enable Control Register 3110Register 7-14: IEC4: Interrupt Enable Control Register 4111Register 7-15: IPC0: Interrupt Priority Control Register 0112Register 7-16: IPC1: Interrupt Priority Control Register 1113Register 7-17: IPC2: Interrupt Priority Control Register 2114Register 7-18: IPC3: Interrupt Priority Control Register 3115Register 7-19: IPC4: Interrupt Priority Control Register 4116Register 7-20: IPC5: Interrupt Priority Control Register 5117Register 7-21: IPC6: Interrupt Priority Control Register 6118Register 7-22: IPC7: Interrupt Priority Control Register 7119Register 7-23: IPC8: Interrupt Priority Control Register 8120Register 7-24: IPC9: Interrupt Priority Control Register 9121Register 7-25: IPC11: Interrupt Priority Control Register 11122Register 7-26: IPC14: Interrupt Priority Control Register 14123Register 7-27: IPC15: Interrupt Priority Control Register 15124Register 7-28: IPC16: Interrupt Priority Control Register 16125Register 7-29: IPC17: Interrupt Priority Control Register 17126Register 7-30: IPC18: Interrupt Priority Control Register 18127Register 7-31: IPC19: Interrupt Priority Control Register 19128Register 7-32: INTTREG: Interrupt Control and Status Register1297.6 Interrupt Setup Procedures1307.6.1 Initialization1307.6.2 Interrupt Service Routine1307.6.3 Trap Service Routine1307.6.4 Interrupt Disable1308.0 Direct Memory Access (DMA)131TABLE 8-1: DMA Channel to Peripheral Associations131FIGURE 8-1: Top Level System Architecture Using a Dedicated Transaction Bus1328.1 DMA Resources1338.1.1 Key Resources1338.2 DMAC Registers133Register 8-1: DMAxCON: DMA Channel x Control Register134Register 8-2: DMAxREQ: DMA Channel x IRQ Select Register135Register 8-3: DMAxSTA: DMA Channel x RAM Start Address Register A(1)136Register 8-4: DMAxSTB: DMA Channel x RAM Start Address Register B(1)136Register 8-5: DMAxPAD: DMA Channel x Peripheral Address Register(1)137Register 8-6: DMAxCNT: DMA Channel x Transfer Count Register(1)137Register 8-7: DMACS0: DMA Controller Status Register 0 (Continued)138Register 8-8: DMACS1: DMA Controller Status Register 1140Register 8-9: DSADR: Most Recent DMA RAM Address1419.0 Oscillator Configuration143FIGURE 9-1: Oscillator System Diagram1439.1 CPU Clocking System1449.1.1 System Clock Sources1449.1.2 System Clock Selection144EQUATION 9-1: Device Operating Frequency1449.1.3 Auxiliary Oscillator1449.1.4 PLL Configuration145EQUATION 9-2: Fosc Calculation145EQUATION 9-3: XT with PLL Mode Example145FIGURE 9-2: dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 and dsPIC33FJ128MCX02/ X04 PLL Block Diagram145TABLE 9-1: Configuration Bit Values for Clock Selection1469.2 Oscillator Resources1469.2.1 Key Resources1469.3 Oscillator Control Registers147Register 9-1: OSCCON: Oscillator Control Register(1,3) (Continued)147Register 9-2: CLKDIV: Clock Divisor Register(2)149Register 9-3: PLLFBD: PLL Feedback Divisor Register(1)150Register 9-4: OSCTUN: FRC Oscillator Tuning Register(2)151Register 9-5: ACLKCON: Auxiliary Clock Divisor Control Register(1)1529.4 Clock Switching Operation1539.4.1 Enabling Clock Switching1539.4.2 Oscillator Switching Sequence1539.5 Fail-Safe Clock Monitor (FSCM)15310.0 Power-Saving Features15510.1 Clock Frequency and Clock Switching15510.2 Instruction-Based Power-Saving Modes15510.2.1 Sleep Mode155EXAMPLE 10-1: PWRSAV Instruction Syntax15510.2.2 Idle Mode15610.2.3 Interrupts Coincident with Power Save Instructions15610.3 Doze Mode15610.4 Peripheral Module Disable15610.5 Power-Saving Resources15710.5.1 Key Resources15710.6 Power-Saving Registers158Register 10-1: PMD1: Peripheral Module Disable Control Register 1 (Continued)158Register 10-2: PMD2: Peripheral Module Disable Control Register 2160Register 10-3: PMD3: Peripheral Module Disable Control Register 316111.0 I/O Ports16311.1 Parallel I/O (PIO) Ports163FIGURE 11-1: Block Diagram of a Typical Shared Port Structure16311.2 Open-Drain Configuration16411.3 Configuring Analog Port Pins16411.4 I/O Port Write/Read Timing16411.5 Input Change Notification164EXAMPLE 11-1: Port Write/Read Example16411.6 Peripheral Pin Select16511.6.1 Available Pins16511.6.2 Controlling Peripheral Pin Select165FIGURE 11-2: remappable MUX input for u1rx165TABLE 11-1: Selectable INPUT SOURCES (MAPS Input TO FUNCTION)(1)166FIGURE 11-3: multiplexing of remappable output for rpn167TABLE 11-2: OUTPUT selection for remappable pin (RPn)16711.6.3 Controlling Configuration Changes16811.7 I/O Helpful Tips16911.8 I/O Resources16911.8.1 Key Resources16911.9 Peripheral Pin Select Registers170Register 11-1: RPINR0: Peripheral Pin Select Input Register 0170Register 11-2: RPINR1: Peripheral Pin Select Input Register 1171Register 11-3: RPINR3: Peripheral Pin Select Input Register 3172Register 11-4: RPINR4: Peripheral Pin Select Input Register 4173Register 11-5: RPINR7: Peripheral Pin Select Input Register 7174Register 11-6: RPINR10: Peripheral Pin Select Input Registers 10175Register 11-7: RPINR11: Peripheral Pin Select Input Register 11176Register 11-8: RPINR12: Peripheral Pin Select Input Register 12176Register 11-9: RPINR13: Peripheral Pin Select Input Register 13177Register 11-10: RPINR14: Peripheral Pin Select INPUT Registers 14178Register 11-11: RPINR15: Peripheral Pin Select Input Register 15179Register 11-12: RPINR16: Peripheral Pin Select INPUT Registers 16180Register 11-13: RPINR17: Peripheral Pin Select Input Register 17181Register 11-14: RPINR18: Peripheral Pin Select Input Register 18182Register 11-15: RPINR19: Peripheral Pin Select Input Register 19183Register 11-16: RPINR20: Peripheral Pin Select Input Register 20184Register 11-17: RPINR21: Peripheral Pin Select Input Register 21185Register 11-18: RPINR22: Peripheral Pin Select Input Register 22186Register 11-19: RPINR23: Peripheral Pin Select Input Register 23187Register 11-20: RPINR26: Peripheral Pin Select Input Register 26(1)187Register 11-21: RPOR0: Peripheral Pin Select Output Register 0188Register 11-22: RPOR1: Peripheral Pin Select Output Register 1188Register 11-23: RPOR2: Peripheral Pin Select Output Register 2189Register 11-24: RPOR3: Peripheral Pin Select Output Register 3189Register 11-25: RPOR4: Peripheral Pin Select Output Register 4190Register 11-26: RPOR5: Peripheral Pin Select Output Register 5190Register 11-27: RPOR6: Peripheral Pin Select Output Register 6191Register 11-28: RPOR7: Peripheral Pin Select Output Register 7191Register 11-29: RPOR8: Peripheral Pin Select Output Register 8(1)192Register 11-30: RPOR9: Peripheral Pin Select Output Register 9(1)192Register 11-31: RPOR10: Peripheral Pin Select Output Register 10(1)193Register 11-32: RPOR11: Peripheral Pin Select Output Register 11(1)193Register 11-33: RPOR12: Peripheral Pin Select Output Register 12(1)19412.0 Timer1195TABLE 12-1: Timer Mode Settings195FIGURE 12-1: 16-bit Timer1 Module Block Diagram19512.1 Timer Resources19612.1.1 Key Resources19612.2 Timer1 Control Register197Register 12-1: T1CON: Timer1 Control Register19713.0 Timer2/3 And TImer4/5199FIGURE 13-1: tYPE b Timer Block Diagram (x = 2 or 4)199FIGURE 13-2: tYPE c Timer Block Diagram (X = 3 OR 5)199TABLE 13-1: Timer Mode Settings20013.1 16-bit Operation20013.2 32-bit Operation200TABLE 13-2: 32-bit Timer200FIGURE 13-3: 32-bit tIMER Block Diagram20113.3 Timer Resources20113.3.1 Key Resources20113.4 Timer Control Registers202Register 13-1: TxCON: Timer Control Register (x = 2 or 4)202Register 13-2: TyCON: Timer Control Register (y = 3 or 5)20314.0 Input Capture205FIGURE 14-1: Input Capture Block Diagram20514.1 Input Capture Resources20614.1.1 Key Resources20614.2 Input Capture Registers207Register 14-1: ICxCON: Input Capture x Control Register (x = 1, 2, 7 or 8)20715.0 Output Compare209FIGURE 15-1: Output Compare Module Block Diagram20915.1 Output Compare Modes210TABLE 15-1: Output Compare Modes210FIGURE 15-2: Output Compare Operation21015.2 Output Compare Resources21115.2.1 Key Resources21115.3 Output Compare Registers212Register 15-1: OCxCON: Output Compare x Control Register (x = 1, 2, 3 or 4)21216.0 Motor Control PWM Module21316.1 PWM1: 6-Channel PWM Module21316.2 PWM2: 2-Channel PWM Module213FIGURE 16-1: 6-Channel PWM Module Block Diagram (PWM1)214FIGURE 16-2: 2-Channel PWM Module Block Diagram (PWM2)21516.3 Motor Control PWM Resources21616.3.1 Key Resources21616.4 PWM Control Registers217Register 16-1: PxTCON: PWM Time Base Control Register217Register 16-2: PxTMR: PWM Timer Count Value Register218Register 16-3: PxTPER: PWM Time Base Period Register218Register 16-4: PxSECMP: Special Event Compare Register219Register 16-5: PWMXCON1: PWM Control Register 1(2)220Register 16-6: PWMxCON2: PWM Control Register 2221Register 16-7: PxDTCON1: Dead-Time Control Register 1222Register 16-8: PxDTCON2: Dead-Time Control Register 2(1)223Register 16-9: PxFLTACON: Fault A Control Register(1)224Register 16-10: PxOVDCON: Override Control Register(1)225Register 16-11: PxDC1: PWM Duty Cycle Register 1226Register 16-12: P1DC2: PWM Duty Cycle Register 2226Register 16-13: P1DC3: PWM Duty Cycle Register 322617.0 Quadrature Encoder Interface (QEI) Module227FIGURE 17-1: Quadrature Encoder Interface Block Diagram (x = 1 or 2)22717.1 QEI Resources22817.1.1 Key Resources22817.2 QEI Control Registers229Register 17-1: QEIxCON: QEIx Control Register (x = 1 or 2) (Continued)229Register 17-2: DFLTxCON: Digital Filter Control Register23118.0 Serial Peripheral Interface (SPI)233FIGURE 18-1: SPI Module Block Diagram23318.1 SPI Helpful Tips23418.2 SPI Resources23418.2.1 Key Resources23418.3 SPI Control Registers235Register 18-1: SPIxSTAT: SPIx Status and Control Register235Register 18-2: SPIxCON1: SPIx Control Register 1 (Continued)236Register 18-3: SPIxCON2: SPIx Control Register 223819.0 Inter-Integrated Circuit™ (I2C™)23919.1 Operating Modes239FIGURE 19-1: I2C™ Block Diagram (x = 1)24019.2 I2C Resources24119.2.1 Key Resources24119.3 I2C Registers241Register 19-1: I2CxCON: I2Cx Control Register (Continued)242Register 19-2: I2CxSTAT: I2Cx Status Register (Continued)244Register 19-3: I2CxMSK: I2Cx Slave Mode Address Mask Register24620.0 Universal Asynchronous Receiver Transmitter (UART)247FIGURE 20-1: UART Simplified Block Diagram24720.1 UART Helpful Tips24820.2 UART Resources24820.2.1 Key Resources24820.3 UART Control Registers249Register 20-1: UxMODE: UARTx Mode Register (Continued)249Register 20-2: UxSTA: UARTx Status and Control Register (Continued)25121.0 Enhanced CAN (ECAN™) Module25321.1 Overview25321.2 Frame Types254FIGURE 21-1: ECAN™ Module Block Diagram25521.3 Modes of Operation25621.3.1 Initialization Mode25621.3.2 Disable Mode25621.3.3 Normal Operation Mode25621.3.4 Listen Only Mode25621.3.5 Listen All Messages Mode25621.3.6 Loopback Mode25621.4 ECAN Resources25721.4.1 Key Resources25721.5 ECAN Control Registers258Register 21-1: CiCTRL1: ECAN™ CONTROL REGISTER 1258Register 21-2: CiCTRL2: ECAN™ Control Register 2259Register 21-3: CiVEC: ECAN™ Interrupt Code Register260Register 21-4: CiFCTRL: ECAN™ FIFO Control Register261Register 21-5: CiFIFO: ECAN™ FIFO Status Register262Register 21-6: CiINTF: ECAN™ Interrupt Flag Register263Register 21-7: CiINTE: ECAN™ Interrupt Enable Register264Register 21-8: CiEC: ECAN™ Transmit/Receive Error Count Register265Register 21-9: CiCFG1: ECAN™ Baud Rate Configuration Register 1265Register 21-10: CiCFG2: ECAN™ Baud Rate Configuration Register 2266Register 21-11: CiFEN1: ECAN™ Acceptance Filter Enable Register267Register 21-12: CiBUFPNT1: ECAN™ Filter 0-3 Buffer Pointer Register267Register 21-13: CiBUFPNT2: ECAN™ Filter 4-7 Buffer Pointer Register268Register 21-14: CiBUFPNT3: ECAN™ Filter 8-11 Buffer Pointer Register268Register 21-15: CiBUFPNT4: ECAN™ Filter 12-15 Buffer Pointer Register269Register 21-16: CiRXFnSID: ECAN™ Acceptance Filter Standard Identifier Register n (n = 0-15)270Register 21-17: CiRXFnEID: ECAN™ Acceptance Filter Extended Identifier Register n (n = 0-15)271Register 21-18: CiFMSKSEL1: ECAN™ Filter 7-0 Mask Selection Register271Register 21-19: CiFMSKSEL2: ECAN™ Filter 15-8 Mask Selection Register272Register 21-20: CiRXMnSID: ECAN™ Acceptance Filter Mask Standard Identifier Register n (n = 0-2)273Register 21-21: CiRXMnEID: ECAN™ Acceptance Filter Mask Extended Identifier Register n (n = 0-2)273Register 21-22: CiRXFUL1: ECAN™ Receive Buffer Full Register 1274Register 21-23: CiRXFUL2: ECAN™ Receive Buffer Full Register 2274Register 21-24: CiRXOVF1: ECAN™ Receive Buffer Overflow Register 1275Register 21-25: CiRXOVF2: ECAN™ Receive Buffer Overflow Register 2275Register 21-26: CiTRmnCON: ECAN™ TX/RX Buffer m Control Register (m = 0,2,4,6; n = 1,3,5,7)27621.6 ECAN Message Buffers27722.0 10-bit/12-bit Analog-to- Digital Converter (ADC1)28122.1 Key Features28122.2 ADC Initialization28122.3 ADC and DMA281FIGURE 22-1: ADC Module Block Diagram FOR dsPIC33FJ32MC304, dsPIC33FJ64MC204/804 and dsPIC33FJ128MC204/804 Devices282FIGURE 22-2: ADC1 Module Block Diagram FOR dsPIC33FJ32MC302, dsPIC33FJ64MC202/802 and dsPIC33FJ128MC202/802 Devices283FIGURE 22-3: ADC Conversion Clock Period Block Diagram28422.4 ADC Helpful Tips28522.5 ADC Resources28522.5.1 Key Resources28522.6 ADC Control Registers286Register 22-1: AD1CON1: ADC1 control register 1 (Continued)286Register 22-2: AD1CON2: ADC1 control register 2288Register 22-3: AD1CON3: ADC1 Control Register 3289Register 22-4: AD1CON4: ADC1 Control Register 4290Register 22-5: AD1CHS123: ADC1 INPUT Channel 1, 2, 3 select Register (Continued)291Register 22-6: AD1CHS0: ADC1 INPUT Channel 0 select Register (Continued)293Register 22-7: AD1CSSL: ADC1 INPUT SCAN SELECT register Low(1,2)295Register 22-8: AD1PCFGL: ADC1 Port configuration register Low(1,2,3)29523.0 Audio Digital-to-Analog Converter (DAC)29723.1 KEY FEATURES29723.2 DAC Module Operation29723.3 DAC Output Format29723.4 DAC CLOCK298FIGURE 23-1: Block Diagram of Audio Digital-to-Analog Converter (DAC)298FIGURE 23-2: Audio DAC output for Ramp Input (Unsigned)29823.5 DAC Resources29923.5.1 Key Resources29923.6 DAC Control Registers300Register 23-1: DAC1CON: DAC Control Register300Register 23-2: DAC1STAT: DAC Status Register301Register 23-3: DAC1DFLT: DAC Default Data Register302Register 23-4: DAC1LDAT: DAC Left Data Register302Register 23-5: DAC1RDAT: DAC Right Data Register30224.0 Comparator Module303FIGURE 24-1: Comparator I/O Operating Modes30324.1 Comparator Resources30424.1.1 Key Resources30424.2 Comparator Control Register305Register 24-1: CMCON: Comparator Control Register (Continued)30524.3 Comparator Voltage Reference30724.3.1 Configuring the Comparator Voltage Reference307FIGURE 24-2: Comparator Voltage Reference Block Diagram307Register 24-2: CVRCON: Comparator Voltage Reference Control Register30825.0 Real-Time Clock and Calendar (RTCC)309FIGURE 25-1: RTCC Block Diagram30925.1 RTCC Module Registers31025.1.1 Register Mapping310TABLE 25-1: RTCVAL Register Mapping310TABLE 25-2: ALRMVAL Register Mapping31025.1.2 Write Lock310EXAMPLE 25-1: Setting the RTCWREN Bit31025.2 RTCC Resources31125.2.1 Key Resources31125.3 RTCC Registers312Register 25-1: RCFGCAL: RTCC Calibration and Configuration RegistER(1) (Continued)312Register 25-2: PADCFG1: Pad Configuration Control Register314Register 25-3: ALCFGRPT: Alarm Configuration Register315Register 25-4: RTCVAL (when RTCPTR<1:0> = 11): YEAR VALUE Register(1)316Register 25-5: RTCVAL (when RTCPTR<1:0> = 10): MONTH AND DAY VALUE Register(1)316Register 25-6: RTCVAL (when RTCPTR<1:0> = 01): WKDYHR: Weekday and Hours Value Register(1)317Register 25-7: RTCVAL (when RTCPTR<1:0> = 00): Minutes and Seconds Value Register317Register 25-8: ALRMVAL (when ALRMPTR<1:0> = 10): Alarm Month and Day Value Register(1)318Register 25-9: ALRMVAL (when ALRMPTR<1:0> = 01): Alarm Weekday and Hours Value Register(1)318Register 25-10: ALRMVAL (when ALRMPTR<1:0> = 00): Alarm Minutes and Seconds Value Register31926.0 Programmable Cyclic Redundancy Check (CRC) Generator32126.1 Overview321EQUATION 26-1: CRC equation321TABLE 26-1: Example CRC Setup321FIGURE 26-1: CRC Shifter Details321FIGURE 26-2: CRC Generator Reconfigured for x16 + x12 + x5 + 132226.2 User Interface32226.2.1 Data Interface32226.2.2 Interrupt Operation32226.3 Operation in Power-Saving Modes32226.3.1 Sleep Mode32226.3.2 Idle Mode32226.4 Programmable CRC Resources32326.4.1 Key Resources32326.5 Programmable CRC Registers324Register 26-1: CRCCON: CRC Control Register324Register 26-2: CRCXOR: CRC XOR Polynomial Register32527.0 Parallel Master Port (PMP)327FIGURE 27-1: PMP Module Overview32727.1 PMP Resources32827.1.1 Key Resources32827.2 PMP Control Registers329Register 27-1: PMCON: Parallel Port Control Register (Continued)329Register 27-2: PMMODE: PARALLEL PORT MODE REGISTER331Register 27-3: PMADDR: Parallel Port Address Register332Register 27-4: PMAEN: Parallel Port Enable Register332Register 27-5: PMSTAT: Parallel Port Status Register333Register 27-6: PADCFG1: Pad Configuration Control Register33428.0 Special Features33528.1 Configuration Bits335TABLE 28-1: Device Configuration Register Map335TABLE 28-2: dsPIC33F Configuration Bits Description (Continued)33628.2 On-Chip Voltage Regulator339FIGURE 28-1: Connections for the On-Chip Voltage Regulator(1,2,3)33928.3 Brown-Out Reset (BOR)33928.4 Watchdog Timer (WDT)34028.4.1 Prescaler/Postscaler34028.4.2 Sleep and Idle Modes34028.4.3 Enabling WDT340FIGURE 28-2: WDT Block diagram34028.5 JTAG Interface34128.6 In-Circuit Serial Programming34128.7 In-Circuit Debugger34128.8 Code Protection and CodeGuard Security341TABLE 28-3: CODE FLASH SECURITY Segment SIZES FOR 32 KB Devices342TABLE 28-4: CODE FLASH SECURITY Segment SIZES FOR 64 KB Devices343TABLE 28-5: CODE FLASH SECURITY Segment SIZES FOR 128 KB Devices34429.0 Instruction Set Summary345TABLE 29-1: Symbols used in Opcode Descriptions (Continued)346TABLE 29-2: Instruction Set OVERVIEW (Continued)34830.0 Development Support35330.1 MPLAB Integrated Development Environment Software35330.2 MPLAB C Compilers for Various Device Families35430.3 HI-TECH C for Various Device Families35430.4 MPASM Assembler35430.5 MPLINK Object Linker/ MPLIB Object Librarian35430.6 MPLAB Assembler, Linker and Librarian for Various Device Families35430.7 MPLAB SIM Software Simulator35530.8 MPLAB REAL ICE In-Circuit Emulator System35530.9 MPLAB ICD 3 In-Circuit Debugger System35530.10 PICkit 3 In-Circuit Debugger/ Programmer and PICkit 3 Debug Express35530.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express35630.12 MPLAB PM3 Device Programmer35630.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits35631.0 Electrical Characteristics357Absolute Maximum Ratings(1)35731.1 DC Characteristics358TABLE 31-1: Operating MIPS vs. Voltage358TABLE 31-2: Thermal Operating Conditions358TABLE 31-3: Thermal Packaging Characteristics358TABLE 31-4: DC Temperature and Voltage specifications359TABLE 31-5: DC Characteristics: Operating Current (Idd)360TABLE 31-6: DC Characteristics: Idle Current (iidle)361TABLE 31-7: DC Characteristics: Power-Down Current (Ipd)362TABLE 31-8: DC Characteristics: doze Current (Idoze)363TABLE 31-9: DC Characteristics: I/O Pin Input Specifications (Continued)364TABLE 31-10: DC Characteristics: I/O Pin Output Specifications367TABLE 31-11: Electrical Characteristics: BOR368TABLE 31-12: DC Characteristics: Program Memory368TABLE 31-13: Internal Voltage Regulator Specifications36831.2 AC Characteristics and Timing Parameters369TABLE 31-14: Temperature and Voltage Specifications – AC369FIGURE 31-1: Load Conditions for Device Timing Specifications369TABLE 31-15: cAPAcITIVE lOADING rEQUIREMENTS ON oUTPUT pINS369FIGURE 31-2: External Clock Timing370TABLE 31-16: External Clock Timing Requirements370TABLE 31-17: PLL Clock Timing Specifications (Vdd = 3.0V to 3.6V)371TABLE 31-18: AC Characteristics: Internal RC Accuracy371TABLE 31-19: Internal RC accuracy371FIGURE 31-3: I/O Timing Characteristics372TABLE 31-20: I/O Timing Requirements372FIGURE 31-4: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing Characteristics373TABLE 31-21: Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer Timing Requirements374FIGURE 31-5: Timer1, 2 and 3 External Clock Timing Characteristics375TABLE 31-22: Timer1 External Clock Timing Requirements(1)375TABLE 31-23: Timer2 and Timer4 External Clock Timing Requirements376TABLE 31-24: Timer3 and Timer5 External Clock Timing Requirements376FIGURE 31-6: TimerQ (QEI Module) External Clock Timing Characteristics377TABLE 31-25: QEI module External Clock Timing Requirements377FIGURE 31-7: INPUT CAPTURE (CAPx) TIMING Characteristics378TABLE 31-26: Input Capture timing requirements378FIGURE 31-8: Output Compare Module (OCx) Timing Characteristics378TABLE 31-27: Output Compare Module timing requirements378FIGURE 31-9: OC/PWM Module Timing Characteristics379TABLE 31-28: Simple OC/PWM MODE Timing Requirements379FIGURE 31-10: Motor Control PWM Module fault Timing Characteristics380FIGURE 31-11: Motor Control PWM Module Timing Characteristics380TABLE 31-29: Motor Control PWM Module Timing Requirements380FIGURE 31-12: QEA/QEB Input Characteristics381TABLE 31-30: Quadrature Decoder Timing Requirements381FIGURE 31-13: QEI Module Index Pulse Timing Characteristics382TABLE 31-31: QEI INDEX PULSE Timing Requirements382TABLE 31-32: SPIx Maximum Data/CLock Rate Summary383FIGURE 31-14: SPIx MASTER MODE (Half-Duplex, Transmit Only CKE = 0) TIMING CHARACTERISTICS383FIGURE 31-15: SPIx MASTER MODE (Half-Duplex, Transmit Only CKE = 1) TIMING CHARACTERISTICS383TABLE 31-33: SPIx Master Mode (Half-Duplex, Transmit Only) Timing Requirements384FIGURE 31-16: SPIx MASTER MODE (Full-Duplex, CKE = 1, CKP = X, SMP = 1) TIMING CHARACTERISTICS385TABLE 31-34: SPIx Master Mode (Full-Duplex, CKE = 1, CKP = x, SMP = 1) Timing Requirements385FIGURE 31-17: SPIx MASTER MODE (Full-Duplex, CKE = 0, CKP = X, SMP = 1) TIMING CHARACTERISTICS386TABLE 31-35: SPIx Master Mode (Full-Duplex, CKE = 0, CKP = x, SMP = 1) Timing Requirements386FIGURE 31-18: SPIx SLAVE MODE (Full-Duplex, CKE = 1, CKP = 0, SMP = 0) TIMING CHARACTERISTICS387TABLE 31-36: SPIx Slave Mode (Full-Duplex, CKE = 1, CKP = 0, SMP = 0) Timing Requirements388FIGURE 31-19: SPIx SLAVE MODE (Full-Duplex, CKE = 1, CKP = 1, SMP = 0) TIMING CHARACTERISTICS389TABLE 31-37: SPIx Slave Mode (Full-Duplex, CKE = 1, CKP = 1, SMP = 0) Timing Requirements390FIGURE 31-20: SPIx SLAVE MODE (Full-Duplex CKE = 0, CKP = 1, SMP = 0) TIMING CHARACTERISTICS391TABLE 31-38: SPIx Slave Mode (Full-Duplex, CKE = 0, CKP = 1, SMP = 0) Timing Requirements392FIGURE 31-21: SPIx SLAVE MODE (Full-Duplex, CKE = 0, CKP = 0, SMP = 0) TIMING CHARACTERISTICS393TABLE 31-39: SPIx Slave Mode (Full-Duplex, CKE = 0, CKP = 0, SMP = 0) Timing Requirements394FIGURE 31-22: I2Cx Bus Start/Stop Bits Timing Characteristics (Master Mode)395FIGURE 31-23: I2Cx Bus Data Timing Characteristics (Master mode)395TABLE 31-40: I2Cx Bus Data Timing Requirements (Master Mode)396FIGURE 31-24: I2Cx Bus Start/Stop Bits Timing Characteristics (slave mode)397FIGURE 31-25: I2Cx Bus Data Timing Characteristics (slave mode)397TABLE 31-41: I2Cx Bus Data Timing Requirements (Slave Mode)398FIGURE 31-26: ECAN Module I/O Timing Characteristics399TABLE 31-42: ECAN Module I/O Timing Requirements399TABLE 31-43: ADC Module Specifications400TABLE 31-44: ADC Module Specifications (12-bit Mode)401TABLE 31-45: ADC Module Specifications (10-bit Mode)402FIGURE 31-27: ADC Conversion (12-bit mode) Timing Characteristics (asam = 0, ssrc<2:0> = 000)403TABLE 31-46: ADC Conversion (12-bit Mode) TiminG rEQUIREMENTS404FIGURE 31-28: ADC Conversion (10-bit mode) Timing Characteristics (chps<1:0> = 01, SIMSAM = 0, asam = 0, ssrc<2:0> = 000)405FIGURE 31-29: ADC Conversion (10-bit mode) Timing cHARACTERISTICS (chps<1:0> = 01, SIMSAM = 0, asam = 1, ssrc<2:0> = 111, SAMC<4:0> = 00001)405TABLE 31-47: ADC CONVERSION (10-bit mode) TIMING rEQUIREMENTS406TABLE 31-48: Audio DAC Module Specifications406TABLE 31-49: Comparator Timing Specifications407TABLE 31-50: Comparator Module Specifications407TABLE 31-51: Comparator Reference Voltage Settling Time Specifications408TABLE 31-52: Comparator Reference Voltage Specifications408FIGURE 31-30: Parallel Slave Port Timing Diagram408TABLE 31-53: Setting Time Specifications409FIGURE 31-31: Parallel Master Port Read Timing DiAgram409TABLE 31-54: Parallel Master Port Read Timing Requirements410FIGURE 31-32: Parallel Master Port Write Timing Diagram410TABLE 31-55: Parallel Master Port Write Timing Requirements411TABLE 31-56: DMA READ/Write Timing Requirements41132.0 High Temperature Electrical Characteristics413Absolute Maximum Ratings(1)41332.1 High Temperature DC Characteristics414TABLE 32-1: Operating MIPS vs. Voltage414TABLE 32-2: Thermal Operating Conditions414TABLE 32-3: DC Temperature and Voltage Specifications414TABLE 32-4: DC Characteristics: Power-down Current (Ipd)415TABLE 32-5: DC Characteristics: Doze Current (Idoze)415TABLE 32-6: DC Characteristics: I/O Pin Output Specifications416TABLE 32-7: DC Characteristics: Program Memory41732.2 AC Characteristics and Timing Parameters418TABLE 32-8: Temperature and Voltage Specifications – AC418FIGURE 32-1: Load Conditions for Device Timing Specifications418TABLE 32-9: PLL Clock Timing Specifications418TABLE 32-10: SPIx Master Mode (cke = 0) Timing Requirements419TABLE 32-11: SPIx Module Master Mode (cke = 1) Timing Requirements419TABLE 32-12: SPIx Module Slave Mode (cke = 0) Timing Requirements420TABLE 32-13: SPIx Module Slave Mode (cke = 1) Timing Requirements420TABLE 32-14: ADC Module Specifications421TABLE 32-15: ADC Module Specifications (12-bit Mode)421TABLE 32-16: ADC Module Specifications (10-bit Mode)422TABLE 32-17: ADC Conversion (12-bit Mode) Timing Requirements423TABLE 32-18: ADC Conversion (10-bit mode) Timing Requirements42332.0 DC and AC Device Characteristics Graphs425FIGURE 32-1: Voh – 2x Driver Pins425FIGURE 32-2: Voh – 4x Driver Pins425FIGURE 32-3: Voh – 8x Driver Pins425FIGURE 32-4: Voh – 16x Driver Pins425FIGURE 32-5: Vol – 2x Driver Pins426FIGURE 32-6: Vol – 4x Driver Pins426FIGURE 32-7: Vol – 8x Driver Pins426FIGURE 32-8: Vol – 16x Driver Pins426FIGURE 32-9: Typical Ipd Current @ Vdd = 3.3V, +85ºC427FIGURE 32-10: Typical Idd Current @ Vdd = 3.3V, +85ºC427FIGURE 32-11: Typical Idoze Current @ Vdd = 3.3V, +85ºC427FIGURE 32-12: Typical Iidle Current @ Vdd = 3.3V, +85ºC427FIGURE 32-13: Typical FRC Frequency @ Vdd = 3.3V428FIGURE 32-14: Typical LPRC Frequency @ Vdd = 3.3V42833.0 Packaging Information42933.1 Package Details430Appendix A: Revision History439Revision A (August 2007)439Revision B (March 2008)439TABLE A-1: Major Section Updates (Continued)439Revision C (May 2009)441TABLE A-2: Major Section Updates (Continued)441Revision D (November 2009)444TABLE A-3: Major Section Updates444Revision E (January 2011)445TABLE A-4: Major Section Updates (Continued)445Revision F (August 2011)448TABLE A-5: Major Section Updates448Revision G (April 2012)448TABLE A-6: Major Section Updates448INDEX449The Microchip Web Site455Customer Change Notification Service455Customer Support455Reader Response456Product Identification System457Dimensioni: 6,25 MBPagine: 460Language: EnglishApri il manuale